ADPLL Phase Detection Using Multiphase Clock Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing all-digital phase locked loop (ADPLL) circuits face challenges in achieving low power consumption and good phase noise while maintaining a compact circuit area, due to the need for a wide detection range in the time-to-digital converter (TDC) which leads to increased circuit area and power consumption, and introduces quantization noise and integral nonlinearity issues.
Innovation Solution
A phase locked loop configuration that includes a digitally controlled oscillation unit, a multiphase clock generation unit, a clock selection unit, a time-to-digital conversion unit, a counter unit, a reference phase generation unit, and a digital loop filter, which allows for a reduced detection range in the TDC by selecting a clock signal close to the reference clock, thereby reducing circuit area and power consumption while maintaining high resolution and suppressing quantization noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the detection range of the time-to-digital converter is increased to cover one period of the feedback clock signal, then precise phase information can be detected, but the circuit area and power consumption increase significantly
Solution Approach 1:
The patent divides the feedback clock signal period into multiple segments by using a counter to generate multiple phase-shifted clock signals. The TDC only needs to detect phase differences within a fraction of the original period, significantly reducing the required detection range and circuit area while maintaining precision through the segmented approach
Solution Approach 2:
The patent introduces a time dimension by using multiple phase-shifted clock signals generated by the counter unit. Instead of detecting the entire period in one dimension, the system uses temporal segmentation where the counter advances through multiple cycles, allowing precise phase measurement across the full period while keeping the TDC detection range small at any given moment
2Measurement precision
If the detection range of the time-to-digital converter is increased to cover one period of the feedback clock signal, then precise phase information can be detected, but power consumption increases
Solution Approach 1:
The TDC operates on a segmented time basis, processing only a fraction of the feedback clock period at each stage. The counter unit divides the measurement task across multiple cycles, allowing the TDC to remain in a low-power state between measurements and reducing overall power consumption while maintaining detection precision
3Measurement precision
If multistage delay elements are linked to increase detection range, then the TDC can cover one period, but integral nonlinearity deteriorates causing fractional spurious
Solution Approach 1:
Instead of using a single long delay line that would accumulate nonlinearity errors, the patent segments the measurement process into multiple short-stage measurements using phase-shifted clocks. Each stage operates within a small detection range where nonlinearity is minimal, and the counter aggregates these measurements to achieve full-period coverage without compounding INL errors
Solution Approach 2:
The system uses periodic clock signals with different phases to repeatedly measure the same phase difference from multiple starting points. This periodic measurement approach allows the system to cover the full period while keeping each individual measurement within the linear range of the delay elements, avoiding the accumulation of nonlinearity errors
4Measurement precision
If the resolution of the time-to-digital converter is increased to lower quantization noise, then measurement precision improves, but circuit area and power consumption increase
Solution Approach 1:
The patent achieves high effective resolution by segmenting the measurement across multiple counter stages rather than requiring a single high-resolution TDC. The counter unit provides fine granularity by counting clock cycles across multiple periods, effectively multiplying the resolution without increasing the physical TDC resolution or its associated area and power consumption
Data Source
AI summary
The present technology relates to a phase locked loop and a control method therefor, which are capable of achieving low power consumption and good phase noise while suppressing the growth of circuit area. The phase locked loop includes: a digitally controlled oscillation unit that controls an oscillation frequency by a control signal in a digital format; a multiphase clock generation unit that generates clock signals with multiple phases synchronized with the digitally controlled oscillation unit; a clock selection unit that selects a selected clock signal out of the clock signals with multiple phases; a time-to-digital conversion unit that detects a time difference between the selected clock signal and a reference clock signal; a counter unit driven by any one clock signal out of the clock signals with multiple phases; a reference phase generation unit that generates a reference phase; a phase comparison unit that compares feedback phase information obtained from an output value of the counter unit and an output value of the time-to-digital conversion unit with the reference phase; and a digital loop filter unit that smooths output of the phase comparison unit and generates the control signal for the digitally controlled oscillation unit.