ADPLL Normalization Circuit for TDC PVT Variation Compensation

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Solution Overview

Problem

All-digital phase-locked loops (ADPLLs) face performance degradation due to varying resolution of time-to-digital converters (TDCs) caused by process-voltage-temperature (PVT) variations, leading to estimation errors that impact overall ADPLL performance.

Innovation Solution

An ADPLL architecture with a normalization circuit that selects optimal gain parameters based on digital output signals to improve TDC linearity, including a calibration method that adjusts gain parameters in real-time using a least mean square (LMS) circuit and candidate gain parameter storage to mitigate resolution variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a TDC is used in an ADPLL, then phase error can be converted into a digital code for processing, but the resolution of the TDC varies due to PVT variations causing estimation errors that impact ADPLL performance

Engineering Contradiction:
ImproveTDC resolutionVSAvoidADPLL performance
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the gain parameter of the TDC based on detected signal characteristics. The normalization circuit modifies the gain parameter to compensate for PVT variations, ensuring consistent TDC resolution across different operating conditions. This resolves the contradiction by making the TDC resolution adaptive rather than fixed, maintaining measurement precision while ensuring reliable ADPLL performance.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If gain parameters are adjusted to improve TDC linearity, then measurement accuracy improves, but system complexity increases due to normalization circuit and calibration requirements

Engineering Contradiction:
ImproveTDC linearityVSAvoidnormalization circuit
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements dynamics by making the gain parameter adjustable rather than fixed. The normalization circuit dynamically selects from multiple candidate gain parameters based on the digital output signal characteristics. This dynamic approach improves TDC linearity while keeping the complexity manageable through a selection mechanism rather than a completely adaptive system.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies segmentation by dividing the gain parameter adjustment into discrete candidate values stored in a lookup table. Instead of continuous adjustment, the normalization circuit selects from segmented gain options, which simplifies the control mechanism while still achieving improved linearity. This segmented approach balances measurement precision improvement with acceptable device complexity.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If multiple candidate gain parameters are stored and selected based on digital output signal, then TDC linearity is improved under various PVT conditions, but memory requirements and selection complexity increase

Engineering Contradiction:
ImproveTDC performance under PVT variationsVSAvoidcandidate gain parameters
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent applies partial action by storing a limited set of candidate gain parameters that cover the expected range of PVT variations. Rather than implementing a fully adaptive system with continuous parameter adjustment, the normalization circuit selects from a partial set of pre-defined gain options. This provides sufficient adaptability for practical operating conditions while minimizing memory requirements and selection complexity.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11838027B2All-digital phase-locked loop and calibration method thereof
Publication Date: 2023.12.05 REALTEK SEMICON CORP
  • US11838027B2 patent drawing
  • US11838027B2 patent drawing
  • US11838027B2 patent drawing

AI summary

An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The TDC is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase difference between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. The normalization circuit selects one of a plurality of candidate gain parameters stored in the normalization circuit in response to the digital output signal, for being utilized as the gain parameter.