ADPLL TDC Observation Window Calibration for Stable Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The time-to-digital converter (TDC) in all-digital phase-locked loops (ADPLLs) for ultra-low-power wireless personal area network (WPAN) radios is power-hungry due to mismatched offset delays, leading to erroneous output codes and performance degradation, including unwanted phase noise and unstable locking.
Innovation Solution
An ADPLL system with a dynamically adjustable offset delay calibration system that evaluates the difference between the first and second offset delays using the TDC output code, generating a delay adjustment control signal to position the observation window correctly, ensuring the TDC operates within the predetermined window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the TDC operates continuously to ensure accurate phase detection, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The TDC is activated periodically only during a predetermined observation window rather than continuously. The enable signal triggers the TDC to operate briefly when phase detection is needed, then it enters a low-power standby state. This periodic operation maintains measurement capability while dramatically reducing average power consumption.
2Use of energy by moving object
If the TDC observation window is narrowed to reduce power consumption, then power consumption is reduced, but reliability deteriorates due to offset delay mismatch
Solution Approach 1:
The system performs preliminary calibration of the observation window position before normal operation. By pre-adjusting the window timing based on measured offset delays, the system ensures the window is correctly positioned to capture the phase transition edge, preventing erroneous readings even with the narrowed window duration.
Solution Approach 2:
The system monitors the TDC output code to detect whether the phase transition edge was successfully captured within the observation window. If an erroneous code is detected (indicating missed edge detection), the system adjusts the observation window timing and retries, ensuring reliable phase detection despite the narrow window.
3Measurement precision
If the TDC observation window is positioned to capture the phase transition edge, then measurement precision is improved, but device complexity increases due to calibration requirements
Solution Approach 1:
The system performs self-calibration by automatically measuring its own offset delays and adjusting the observation window position accordingly. The calibration routine uses the existing TDC and enable signal infrastructure to measure delays and compute the correct window timing, eliminating the need for external calibration equipment or complex manual adjustment mechanisms.
Data Source
AI summary
An all-digital-phase-locked-loop (ADPLL) includes a digitally controlled oscillator (DCO) arranged to generate a DCO output signal, and a feedback loop comprising a set of components for controlling the DCO. The set of components comprise: a time-to-digital converter (TDC) arranged to generate a TDC output code indicative of the phase difference between the reference signal and the enable signal measured within the predetermined observation window; a subset of components arranged to generate the enable signal from the DCO output signal; and an offset calibration system connected to the TDC output, which when activated is arranged to evaluate the difference between the first and second offset delay values by monitoring the TDC output code generated over a predetermined period of time, and to adjust the difference to position the predetermined observation window with respect to the reference signal.