ADPLL Phase Detection with Offset Loop Near Zero Error
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Solution Overview
Problem
ADPLLs face challenges in accurately detecting phase differences near zero degrees due to limitations in resolution, detection range, linearity, and occupation area, particularly in RF-ICs, which affect the noise performance and efficiency of phase-locked loops.
Innovation Solution
The introduction of an offset value in the loop of the ADPLL circuit, combined with a digitally controlled oscillator and a delay-line configuration, enhances phase difference detection precision and range, ensuring accurate phase difference measurement even at low through rates, thereby improving noise performance and reducing circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the analog circuit is replaced with a digital circuit in RF-ICs, then the consumption current and area are reduced, but the phase difference detection precision near zero degrees deteriorates
Solution Approach 1:
The phase difference detection function is segmented into two independent TDC circuits: a first TDC for detecting phase difference in a first range and a second TDC for detecting phase difference in a second range. This segmentation allows each TDC to be optimized for its specific detection range, maintaining high precision near zero degrees while keeping the overall circuit digital and low-power.
Solution Approach 2:
The system dynamically switches between the first TDC and the second TDC based on the detected phase difference range. When the phase difference is near zero degrees, the first TDC is used for high-precision detection; when it exceeds a threshold, the second TDC takes over. This dynamic adaptation maintains detection precision across all ranges while preserving the low-power digital architecture.
2Measurement precision
If the detection range of TDC is increased, then the phase difference detection capability is improved, but the occupation area increases
Solution Approach 1:
The detection range is segmented into two ranges handled by separate TDC circuits. The first TDC covers a smaller range with higher precision near zero degrees, while the second TDC covers a wider range. This segmentation allows the occupation area to be optimized for each function rather than requiring one large TDC to handle all ranges.
Solution Approach 2:
The first TDC is designed with sufficient precision for small phase differences near zero degrees, which is the critical detection range. The second TDC handles larger phase differences with less stringent precision requirements. This partial action approach ensures high precision where needed while minimizing the occupation area of each individual TDC circuit.
3Measurement precision
If the resolution of TDC is improved, then the phase difference detection precision is enhanced, but the number of delay devices and DFFs increases
Solution Approach 1:
The high-resolution detection task is segmented and assigned to the first TDC, which uses a manageable number of delay devices and DFFs optimized for small phase differences. The second TDC handles larger phase differences with fewer resources. This segmentation allows the first TDC to achieve high resolution without requiring an excessive total number of delay devices and DFFs across the entire system.
Solution Approach 2:
The first TDC is locally optimized with higher resolution (more delay devices and DFFs) specifically for the critical region near zero degrees phase difference, where precision is most important. The second TDC uses a simpler configuration suitable for larger phase differences. This local quality approach concentrates resources where they provide the most value, improving overall detection precision without uniformly increasing device complexity throughout the system.
Data Source
AI summary
In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.