ADPLL Phase Converter Using Sub-Period Fractional Phase Detection
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Solution Overview
Problem
Conventional time-to-digital converters (TDCs) in all-digital phase-locked loops (ADPLLs) require complex circuit structures and high operational frequencies to achieve high resolution, leading to inefficiencies in phase detection and frequency synchronization.
Innovation Solution
The proposed solution involves a phase converter module with a fast phase finder and a precise time-to-digital converter that divides the oscillation period into N sub-periods, allowing the phase finder to estimate the fractional phase part and the time-to-digital converter to calculate a precise value within one sub-period, reducing the complexity and frequency requirements of the TDC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional TDCs use complex circuit structures and high operational frequencies to achieve high resolution, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The oscillation period is divided into N sub-periods, and the phase detection process is segmented into two stages: a fast phase finder that identifies the coarse phase region, and a TDC that precisely measures the fine phase within that region. This segmentation allows the TDC to operate at lower frequencies with reduced complexity while maintaining high overall resolution.
Solution Approach 2:
The fast phase finder performs preliminary phase estimation before the TDC measurement. By pre-identifying the correct sub-period and providing an initial phase estimate, the phase finder eliminates the need for the TDC to search through the entire oscillation period, thereby reducing the TDC's operational frequency requirements and circuit complexity.
2Measurement precision
If conventional TDCs operate at high frequencies to achieve high resolution, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The phase detection function is segmented between the fast phase finder and the TDC. The phase finder handles the energy-intensive coarse search at lower frequencies, while the TDC operates at reduced frequencies for fine measurement, thereby reducing overall energy consumption while maintaining high resolution.
Solution Approach 2:
The phase finder performs preliminary phase estimation that eliminates the need for high-frequency TDC operation. By pre-localizing the phase within one sub-period, the TDC can operate at lower frequencies, significantly reducing energy consumption while preserving measurement precision.
3Measurement precision
If conventional TDCs use complex circuit structures to achieve high resolution, then measurement precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The phase detection system is segmented into a fast phase finder using simple logic circuits and a TDC with reduced complexity. This segmentation enables easier manufacturing by replacing complex high-frequency TDC circuits with simpler low-frequency circuits, while the phase finder uses straightforward combinatorial logic that is easier to manufacture.
Solution Approach 2:
The phase finder performs preliminary phase estimation using simple logic operations before the TDC measurement. This preliminary action allows the TDC to operate at lower frequencies with simpler circuitry, improving ease of manufacture while maintaining high measurement precision through the combined two-stage approach.
Data Source
AI summary
A phase-locked loop circuit, a phase converter module thereof and a phase-locked controlling method are disclosed herein. The phase converter module is suitable for a phase-locked loop circuit including a digitally-controlled oscillator (DCO) for generating an oscillator output signal and a divider for converting the oscillator output signal into N-phased oscillator output signals. The phase converter module includes a phase finder and a time-to-digital converter. The phase finder is configured for sampling the oscillator output signal with the N-phased oscillator output signals to calculate an estimated value of a fractional phase part. One oscillation period of the digitally-controlled oscillator is divided into N sub-periods. The time-to-digital converter is configured for sampling one of the N-phased oscillator output signals with a reference-frequency signal to calculate a precise value of the fractional phase part within one sub-period.