Fractional-N ADPLL Reference Dithering for Spur Reduction
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Solution Overview
Problem
Fractional-N all-digital phase locked loops (ADPLLs) are prone to spurious tones in their output spectrum, particularly when the ratio of output to input frequency is close to an integer value, which limits their application in various systems.
Innovation Solution
The introduction of a randomly modulated delay with a triangular distribution, added via a variable delay line, dithers the phase of the reference frequency at the input of the fractional-N ADPLL, effectively reducing spurious tones without requiring active control or calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fractional-N ADPLL is used to achieve frequency ratios close to integer values, then frequency resolution is improved, but spurious tones appear in the output spectrum
Solution Approach 1:
The patent applies dithering technology to convert the harmful quantization effects that cause spurious tones into beneficial randomization. By adding controlled random noise to the reference frequency signal, the periodic quantization errors are transformed into random errors with lower spectral density, effectively reducing spurious tones while maintaining frequency resolution
Solution Approach 2:
The patent modifies the reference frequency parameter by applying a random dither signal with triangular distribution. This changes the reference frequency from a fixed value to a dynamically varying parameter, which prevents the regular quantization patterns that generate spurious tones in fractional-N ADPLLs
2Object-generated harmful factors
If dithering is applied to reduce spurious tones, then noise performance is improved, but device complexity increases
Solution Approach 1:
The patent uses a simple triangular distribution generator based on uniform random number generation, which is computationally inexpensive and easy to implement. The dither signal is generated using basic arithmetic operations on uniformly distributed random numbers, avoiding complex hardware or algorithms while effectively reducing spurious tones
Data Source
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AI summary
A fractional-N all digital phase locked loop (ADPLL) includes a randomly modulated delay having a triangular distribution to a frequency reference at an input of the fractional-n ADPLL to reduce spurious tones introduced by delta-sigma modulation of a frequency control word without requiring active control or calibration. In some embodiments, a delay line generates the randomly modulated delay based on a uniformly distributed random number with a flat spectrum that is shaped by a high pass filter.