ADPLL Clock Synchronization Using PFD Switching to Cut Noise
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Solution Overview
Problem
In frequency divider based ADPLLs, clock synchronization between a reference clock and a divider clock introduces metastability and increases noise due to asynchronous operation during phase locking and tracking stages.
Innovation Solution
Implementing a two-flop synchronizer and phase frequency detector (PFD) in the ADPLL to manage clock synchronization, using a synchronization control circuit to switch between phase locking and tracking states, reducing metastability and noise through controlled PFD operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock synchronization is implemented between reference clock and divider clock, then phase locking is achieved, but metastability and noise increase
Solution Approach 1:
The patent applies preliminary action by performing clock synchronization only when necessary (during mode transitions) rather than continuously. The synchronization control circuit activates the synchronizer only when switching between frequency division modes, preventing continuous metastability issues while ensuring phase alignment is achieved before tracking begins.
Solution Approach 2:
The patent implements dynamic operation by making the synchronization circuit controllable and switchable. The synchronization control circuit dynamically enables or disables the synchronizer based on the operational mode of the ADPLL, allowing the system to adapt between synchronization and tracking modes to minimize noise while maintaining reliability.
2Stability of the object's composition
If continuous synchronization is performed during phase tracking, then phase relation is maintained, but integrated CP noise increases
Solution Approach 1:
The patent applies periodic action by performing synchronization only at specific intervals (during mode transitions) rather than continuously. The synchronization control circuit triggers the synchronizer periodically when needed, allowing the phase relation to be maintained through controlled, intermittent synchronization events rather than continuous operation.
Solution Approach 2:
The patent extracts the synchronization function from continuous operation and separates it into discrete, controlled events. By using the synchronization control circuit to isolate and activate the synchronizer only when necessary, the harmful continuous noise generation is eliminated while the essential phase relation maintenance function is preserved at critical moments.
Data Source
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AI summary
Embodiments of a clock synchronization unit of an All Digital Phase-Locked Loop (ADPLL), a successive approximation register (SAR) Time-to-Digital Converter (TDC) of an ADPLL and a method for clock synchronization in an ADPLL are disclosed. In one embodiment, a clock synchronization unit of an ADPLL includes a two-flop synchronizer, a phase frequency detector (PFD) connected to the two-flop synchronizer, and a synchronization control circuit configured to control the two-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal and to control the two-flop synchronizer and the PFD to replace a performance of the clock synchronization between the reference clock input signal and the divided clock input signal with a PFD operation. Other embodiments are also described.