ADPLL TDC Gain Calibration for PVT-Stable Phase Measurement
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Solution Overview
Problem
The resolution of a time-to-digital converter (TDC) in all-digital phase-locked loops (ADPLLs) varies due to process-voltage-temperature (PVT) variations, affecting the performance of ADPLLs by introducing estimation errors in parameter settings.
Innovation Solution
An ADPLL architecture with a normalization circuit that modifies the gain parameter based on phase error values between the clock and reference signals, using a feedback calibration mechanism to converge the gain parameter to a correct value, thereby addressing the resolution variability of the TDC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a TDC is used as a phase detector in an ADPLL, then the phase error can be converted into a digital code for digital domain processing, but the resolution of the TDC varies due to PVT variations, introducing estimation errors in parameter settings
Solution Approach 1:
The patent implements a feedback calibration mechanism where the normalized phase error is fed back to adjust the gain parameter of the TDC. The normalization circuit calculates the actual phase error and compares it with the expected value, generating a correction signal that adjusts the TDC gain to compensate for PVT variations, thereby maintaining measurement precision
Solution Approach 2:
The patent dynamically changes the gain parameter of the TDC based on detected phase errors. By adjusting this parameter in response to PVT variations, the system maintains accurate phase measurement despite environmental changes, resolving the contradiction between operational flexibility and measurement precision
2Measurement precision
If the gain parameter of the TDC is adjusted to compensate for resolution variations, then the measurement precision can be maintained under PVT variations, but the device complexity increases due to the need for calibration mechanisms
Solution Approach 1:
The normalization circuit performs self-calibration by using its own output (the normalized phase error) to adjust the TDC gain parameter. This self-service mechanism eliminates the need for external calibration equipment or complex control circuits, maintaining measurement precision while minimizing device complexity
Solution Approach 2:
The patent merges the normalization function and the gain calibration function into a single integrated circuit. By combining these functions, the system achieves accurate TDC gain adjustment without requiring separate calibration circuits, thereby reducing overall device complexity while maintaining measurement precision
Data Source
AI summary
An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The DCO is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase error between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. More particularly, the normalization circuit may modify the gain parameter according to a phase error value between the clock phase value and a reference phase value.