ADPLL TDC Offset Calibration for Low-Power Stable Locking
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Solution Overview
Problem
The Time-to-Digital Converter (TDC) in All-Digital Phase-Locked Loops (ADPLLs) is power-hungry due to its high activity, and traditional methods to reduce power consumption, such as snapshotting, can lead to erroneous outputs if the offset delays are mismatched, causing phase noise and unstable locking.
Innovation Solution
An ADPLL system with a dynamically adjustable offset delay calibration system that evaluates the difference between the first and second offset delays using the TDC output code, adjusting these delays to ensure the TDC operates within a predetermined observation window, thereby ensuring accurate phase detection and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the TDC operates continuously with high activity to ensure accurate phase detection, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The TDC is operated periodically rather than continuously by using a snapshot mechanism that activates the TDC only during a brief observation window when the delayed reference clock edge arrives, significantly reducing power consumption while maintaining measurement capability
Solution Approach 2:
The delayed reference clock signal is prepared in advance with a predetermined delay to align with the expected arrival time of the DCO output edge, enabling the TDC to be activated at the precise moment needed for accurate phase measurement
2Use of energy by moving object
If the TDC observation window is narrowed to reduce power consumption, then power consumption is reduced, but reliability deteriorates due to timing mismatches
Solution Approach 1:
The system incorporates an offset calibration mechanism that uses feedback from the TDC output to dynamically adjust the delay of the delayed reference clock signal, ensuring that the narrow observation window remains properly aligned with the DCO output edge despite variations in operating conditions
Solution Approach 2:
The offset delay of the reference clock is made dynamically adjustable through a calibration system that can modify the delay value based on detected timing errors, allowing the observation window to adapt to changing conditions and maintain reliability
3Device complexity
If offset delays are fixed to simplify the design, then device complexity is reduced, but manufacturing precision deteriorates due to PVT variations
Solution Approach 1:
The offset delay parameter of the reference clock signal is made changeable through a calibration system that adjusts the delay value based on detected timing errors, allowing the system to compensate for manufacturing variations and PVT effects without fundamentally changing the TDC architecture
Data Source
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Figure 3(a)~3(b)
AI summary
An All-Digital-Phase-Locked-Loop (ADPLL) (10), comprising a Digitally Controlled Oscillator (DCO) (11) arranged for generating a DCO output signal, and a feedback loop comprising a set of components for controlling the DCO (11). The components comprising: a Time-to-Digital Converter (15), TDC, arranged for generating a TDC output code indicative of the phase difference between the reference signal and the enable signal measured within the predetermined observation window; and a subset of components arranged for generating the enable signal from the DCO output signal. The set of components of the feedback loop comprises an offset calibration system, connected to the TDC output, which when activated is arranged for evaluating the difference between the first and second offset delay values by monitoring the TDC output code generated over a predetermined period of time and for adjusting said difference to position the predetermined observation window with respect to the reference signal.