ADPLL Voltage Doubler Control for Stable TDC Resolution

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Solution Overview

Problem

All-digital phase locked loops (ADPLLs) face fluctuations in time-to-digital converter (TDC) resolution due to process, voltage, and temperature (PVT) variations, leading to varying in-band phase noise.

Innovation Solution

Incorporating voltage doubler circuitry to scale the analog input supply voltage and calibration circuitry to regulate the digital input supply voltage, stabilizing the TDC resolution across PVT variations through a switching clocking signal that adjusts the charging and discharging of switched capacitors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If voltage scaling is performed to operate both analog and digital circuitry from a single supply, then device complexity is reduced, but TDC resolution fluctuates due to PVT variations

Engineering Contradiction:

Improvesupply voltage architectureVSAvoidTDC resolution

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent implements dynamic voltage regulation by monitoring TDC resolution and adjusting the digital circuitry supply voltage in real-time. The calibration circuitry dynamically scales the voltage to maintain optimal TDC resolution across PVT variations, transforming a static voltage supply into a dynamic, adaptive system that compensates for environmental changes.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system employs feedback mechanisms where the TDC resolution is continuously monitored and used to control the voltage regulation. The calibration circuitry receives feedback about resolution deviations and adjusts the supply voltage accordingly, creating a closed-loop control system that maintains stable TDC performance despite PVT variations.

Inventive Principle:

Principle #23Feedback

2Ease of manufacture

If a single analog input supply voltage is used for both analog and digital circuitry, then ease of manufacture is improved, but in-band phase noise varies across PVT conditions

Engineering Contradiction:

Improvesupply voltage configurationVSAvoidin-band phase noise consistency

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the supply voltage architecture by creating separate regulated voltage domains for analog and digital circuitry. While both domains originate from a single analog input supply, the digital circuitry receives a separately regulated voltage through the voltage doubler and calibration circuitry, allowing independent optimization of each domain's performance characteristics.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system changes the voltage parameter dynamically by adjusting the digital circuitry supply voltage based on monitored TDC resolution. This parameter adjustment compensates for PVT variations and maintains consistent in-band phase noise performance across different operating conditions while keeping the manufacturing process simple.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Maintains a fixed in-band phase noise across PVT variations by stabilizing the TDC resolution, ensuring consistent ADPLL performance.

Implementation Method 1

voltage doubler circuitry to scale the analog input supply voltage

Methodology Applied

Scientific EffectVoltage doubling:

Implementation Method 2

The voltage doubler circuitry charges or discharges one or more switchable capacitors in accordance with a switching clocking signal

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentUS10326454B2All-digital phase locked loop using switched capacitor voltage doubler

Publication Date: 2019.06.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.