ADPLL Phase Difference Detection with Offset Locking Near Zero
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Solution Overview
Problem
ADPLLs face challenges in phase difference detection near zero degrees due to limitations in resolution, detection range, linearity, and occupation area, particularly in RF-ICs where high precision and low noise are required, especially in systems with phase modulation.
Innovation Solution
The introduction of an offset value in the loop of the ADPLL circuit to ensure a constant phase difference between reference and feedback signals, combined with a counter and delay-line configuration for precise phase difference measurement, enhances detection near zero degrees and improves overall performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the phase difference detection range is increased to cover zero degrees, then the detection capability near zero is improved, but the resolution and linearity deteriorate due to the tradeoff relationship among resolution, detection range, linearity, and occupation area
Solution Approach 1:
The phase difference detection range is divided into two segments: a first range centered around zero degrees (from -Δθ to +Δθ) and a second range covering the remaining phase differences. The first segment uses a first TDC with optimized resolution for near-zero detection, while the second segment uses a second TDC with coarser resolution. This segmentation allows each segment to be optimized for its specific function, resolving the contradiction between detection capability near zero and linearity across the full range.
Solution Approach 2:
Different detection qualities are applied to different regions of the phase difference range. The first TDC provides high-resolution detection for the critical near-zero region, while the second TDC provides sufficient detection for larger phase differences. This local quality approach ensures that resources are concentrated where they are most needed (near zero) without compromising overall system performance.
2Measurement precision
If the detection range is expanded to include zero degrees, then the phase difference detection near zero is improved, but the occupation area increases
Solution Approach 1:
The detection system is segmented into two TDCs with different detection ranges and resolutions. The first TDC handles the narrow near-zero range with high resolution, requiring minimal area, while the second TDC handles the broader range with coarser resolution, also requiring less area than a single high-resolution TDC would need to cover the entire range. This segmentation reduces the total occupation area while maintaining detection capability near zero.
3Measurement precision
If the resolution is increased to improve detection near zero, then the phase difference detection precision is improved, but the detection range and occupation area increase due to the tradeoff relationship
Solution Approach 1:
The high-resolution detection capability is segmented to apply only to the near-zero phase difference range where it is most critical. The first TDC provides high resolution for small phase differences, while the second TDC provides coarser resolution for larger phase differences. This segmentation allows the system to achieve high detection precision near zero without the area penalty of a uniformly high-resolution system.
Data Source
AI summary
In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.