Array Substrate Gate Insulation Segmentation for ADS-LCD
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Solution Overview
Problem
The complex fabrication process and poor driving effect, along with low light transmittance, in array substrates of Advanced Super Dimension Switch (ADS) mode liquid crystal display devices due to the need for multiple patterning processes and the presence of a gate insulation layer between electrodes.
Innovation Solution
A method of fabricating array substrates where the gate insulation layer is formed only on the gate and gate line, allowing the source and drain to be electrically connected through vias, and the second transparent electrode is positioned above the passivation layer, reducing the distance between electrodes and eliminating the gate insulation layer between them, thus simplifying the process to two exposures and enhancing conductivity and light transmittance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate insulation layer is formed on the whole substrate base including between electrodes, then the insulation performance is improved, but the distance between electrodes increases and light transmittance decreases
Solution Approach 1:
The gate insulation layer is segmented into two regions: one covering the gate electrode and gate line for insulation, and another removed region between the first and second transparent electrodes to reduce distance and improve light transmittance. This segmentation allows simultaneous achievement of insulation performance and optical performance.
Solution Approach 2:
The gate insulation layer is selectively removed only in the region between the first transparent electrode and second transparent electrode, while maintaining the insulation layer in other regions. This local modification optimizes the specific area requiring high light transmittance without compromising overall insulation performance.
2Manufacturing precision
If photolithography is performed at least six times to fabricate gate, gate line, semiconductor layer, first transparent electrode, source, drain and second transparent electrode, then the fabrication precision is improved, but the process complexity increases
Solution Approach 1:
Multiple patterning steps are merged into fewer steps by using a color separation technique where different structures (gate, gate line, semiconductor layer, first transparent electrode, source, drain, and second transparent electrode) are formed through integrated photolithography processes with selective photoresist removal, reducing the total number of photolithography cycles from six or more to a smaller number while maintaining patterning precision.
3Reliability
If the gate insulation layer covers the whole substrate base, then the insulation performance is improved, but the electric field intensity and capacitance decrease
Solution Approach 1:
The gate insulation layer is segmented to provide insulation where needed (over gate and gate line) while removing it in the region between transparent electrodes to enhance electric field intensity and capacitance for improved driving performance.
Data Source
AI summary
An array substrate, a method of fabricating the same, and a liquid crystal display device are disclosed. The method comprises: sequentially forming a first transparent conductive material layer, an insulation material layer, a semiconductor material layer and a photoresist layer on a substrate base and forming patterns including a gate line, a gate, a gate insulation layer, a semiconductor layer and a first transparent electrode by patterning process; forming a passivation layer and forming a source via and a drain via connected to the semiconductor layer in the passivation layer; sequentially forming a second transparent conductive material layer and a source-drain metal layer and forming patterns including a source, a drain and a second transparent electrode by patterning process, the gate insulation layer is formed only on the gate and the gate line, the source and the drain include stacked second transparent conductive material layer and source-drain metal layer.