Advance Correlating Notification for Branch Target Prediction
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Solution Overview
Problem
Indirect branch instructions in processor pipelines often lead to mispredictions, reducing processor performance due to the difficulty in predicting branch target addresses derived from registers, which causes incorrect speculative execution and increased power consumption from flushing unnecessary instructions.
Innovation Solution
The introduction of an Advance Correlating Notification (ADVCN) instruction that specifies a register value correlating to the target address, allowing for speculative fetching of instructions based on predicted storage addresses before the execution of branch instructions, thereby minimizing mispredictions and improving processor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If speculative execution is used to fetch and execute instructions at a predicted branch target address, then processor performance is improved, but mispredictions cause incorrect speculative execution and increased power consumption from flushing unnecessary instructions
Solution Approach 1:
The patent applies preliminary action by introducing an ADVCN instruction that provides advance notification of the branch target address before the actual branch instruction is executed. This allows the processor to pre-fetch instructions at the predicted target address in advance, reducing the need for pipeline flushing when mispredictions occur and thereby decreasing power consumption while maintaining speculative execution benefits
2Adaptability or versatility
If indirect branch instructions are used to branch to addresses derived from register contents, then programming flexibility is improved, but prediction accuracy deteriorates because the register may have different values each time the instruction is executed
Solution Approach 1:
The patent uses an intermediary approach by introducing a dedicated ADVCN instruction as a mediator between the branch instruction and the prediction mechanism. This ADVCN instruction explicitly provides the branch target address or the register whose value determines the target address, serving as an intermediary that bridges the flexibility of indirect branching with the accuracy needs of prediction algorithms
3Reliability
If branch target address prediction is improved by using ADVCN instructions, then misprediction rate is reduced, but device complexity increases due to additional instruction and circuit requirements
Solution Approach 1:
The patent applies universality by designing the ADVCN instruction to serve multiple functions: it can provide advance notification of branch target addresses for various types of branches (direct, indirect, conditional), work with different branch prediction algorithms, and be integrated into existing processor pipelines. This multi-functionality reduces the need for separate specialized circuits for each prediction scenario
Data Source
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Figure 3A~3B
AI summary
Apparatus and techniques for predicting a storage address based on contents of a first program accessible register (PAR) specified in a first instruction, wherein the first PAR correlates with a target address specified by a second PAR in a second instruction. Information is speculatively fetched at the predicted storage address prior to execution of the second instruction. The first instruction is an advance correlating notification (ADVCN) instruction, the second instruction is an indirect branch instruction, and the information is a plurality of instructions beginning at the predicted storage address. The predicted storage address is a branch target address for the indirect branch instruction from which instructions are speculatively fetched. The prediction is based on contents of the first PAR specified in the ADVCN instruction. The contents of the first PAR correlate with a taken evaluation of the branch instruction.