Advanced Node Interconnect Layout for Routing Density Limits
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Solution Overview
Problem
The miniaturization of integrated circuits leads to challenges in providing sufficient routing resources due to limitations in metal pitch, which restricts the number of metal tracks within a given cell height, hindering the achievement of minimum cell and chip area, especially at advanced nodes like the N2 node with transistors having gate lengths less than 2 nanometers.
Innovation Solution
The proposed solution involves layout designs that optimize metal pattern structures by reducing the number of M2 tracks within a cell height while maintaining sufficient routing resources, using one mask per metal layer without additional cuts, and employing double cell height configurations to accommodate increased transistor density, allowing for efficient signal and power routing without design rule violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of M2 tracks is increased to provide sufficient routing resources, then routing capability is improved, but cell height increases preventing minimum cell area achievement
Solution Approach 1:
The patent transitions from horizontal routing (within a single cell height) to vertical routing (utilizing multiple metal layers M0-M6). By stacking metal tracks across multiple layers and using via connections, the design achieves sufficient routing capacity without increasing cell height, effectively moving the routing solution from a 2D plane to a 3D structure.
Solution Approach 2:
The patent implements nested routing where multiple routing paths are embedded within the vertical stack of metal layers. Each metal layer contains tracks that can be accessed through via connections, creating a nested hierarchy of routing resources that maximizes connectivity within the constrained cell height.
2Quantity of substance
If metal pitch is reduced to fit more tracks, then routing density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the critical parameter from metal pitch (horizontal spacing) to layer thickness and via dimensions (vertical spacing). By controlling the thickness of interlayer dielectric layers and via hole dimensions rather than horizontal metal track spacing, the design achieves high routing density while maintaining manufacturability at advanced nodes like N2.
3Area of stationary object
If cell height is reduced to achieve minimum area, then area efficiency is improved, but routing resource allocation becomes insufficient
Solution Approach 1:
The patent resolves this contradiction by adding the vertical dimension to routing resource allocation. Instead of relying solely on horizontal space within a compressed cell height, the design utilizes multiple metal layers stacked vertically, providing abundant routing resources within the reduced cell area through 3D spatial utilization.
4Adaptability or versatility
If additional mask cuts are used to create complex metal patterns, then routing flexibility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the routing function across multiple metal layers, with each layer handling specific routing tasks. This segmentation allows standard patterning processes to be applied to each layer independently, achieving complex overall routing flexibility without requiring additional mask cuts within individual layers, thus maintaining manufacturing simplicity.
Data Source
AI summary
A method for fabricating an integrated circuit includes forming a first pattern metal layer comprising a plurality of metal tracks extending in a first direction. Each of the plurality of metal tracks is separated from its adjacent one of the plurality of metal tracks by a first pitch. The method further includes forming a second pattern metal layer formed over the first pattern metal layer. The second pattern metal layer comprises a second plurality of metal tracks extending in the first direction. Each of the second plurality of metal tracks is separated from its adjacent one of the second plurality of metal tracks by a second pitch. The method further includes forming a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer.