Advanced Register Merging in Logic Synthesis
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Solution Overview
Problem
Existing logic synthesis systems face challenges in efficiently determining complex register equivalences, leading to high runtime overhead and inadequate formal verification of equivalences found during the synthesis process.
Innovation Solution
A computer-implemented logic synthesis method that performs advanced register merging by loading an RTL description and using multiple register-merging operations to identify and verify functional equivalences among registers, employing satisfiability checks and random simulations to reduce runtime and improve verification efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sophisticated functional equivalence checking is performed to find all complex register equivalences, then the completeness of equivalence detection is improved, but the runtime overhead increases significantly
Solution Approach 1:
The patent segments the equivalence checking process into multiple phases: initial net-based equivalence detection, functional equivalence checking for candidate pairs, and formal verification. This segmentation allows the system to quickly identify obvious equivalences without exhaustive checking, reducing runtime while maintaining completeness for complex cases.
Solution Approach 2:
The patent applies different checking strategies to different register pairs based on their characteristics. Simple register pairs use fast net-based equivalence, while complex candidates undergo functional equivalence checking. This local differentiation optimizes the balance between detection completeness and runtime efficiency.
2Loss of time
If simple net-based equivalence checking is used, then the runtime overhead is reduced, but the ability to detect complex register equivalences is insufficient
Solution Approach 1:
The patent performs preliminary net-based equivalence checking to quickly identify and merge obviously equivalent registers before conducting more sophisticated functional equivalence checking. This preliminary action reduces the search space for complex equivalences, maintaining runtime efficiency while enabling deeper detection capability.
Solution Approach 2:
The patent introduces an intermediary functional equivalence checking phase that bridges the gap between simple net-based checking and exhaustive formal verification. This intermediary layer uses targeted functional analysis to detect complex equivalences that net-based methods miss, without requiring full formal verification of all register pairs.
3Measurement precision
If exhaustive functional equivalence checking is performed on all register pairs, then all complex equivalences are found, but the verification time becomes prohibitively long
Solution Approach 1:
The patent performs partial functional equivalence checking on selected candidate register pairs rather than exhaustive checking of all pairs. By identifying candidates through net-based equivalence and targeted functional analysis, the system achieves sufficient verification throughput while detecting the majority of complex equivalences without prohibitively long verification times.
4Reliability
If multiple phases of register merging are performed with formal verification, then the reliability of equivalence results is improved, but the overall processing time increases
Solution Approach 1:
The patent performs preliminary merging of obviously equivalent registers using net-based equivalence before conducting formal verification on remaining candidates. This preliminary action reduces the number of registers requiring formal verification, maintaining reliability while reducing overall processing time.
Solution Approach 2:
The patent segments verification into targeted formal verification of candidate equivalence classes rather than verification of all register pairs. This segmentation maintains reliability for complex equivalences while significantly reducing the total verification burden and processing time.
Data Source
AI summary
Disclosed herein are computer-implemented method, system, and computer-program product (non-transitory computer-readable storage medium) embodiments for advanced register merging. A first register-merging operation may be configured to merge, into a first survivor register, a first plurality of registers of the RTL description. A second register-merging operation configured to merge, into a first equivalence class, a second plurality of registers that share a first functional equivalency based on output of the first register-merging operation. Any register in the first equivalence class as noted here may in turn be non-equivalent to any register in the second equivalence class. Equivalence of registers in a given class may be verified using simulations or satisfiability checks.