AEAD Instruction Authentication on Cache Miss Using Golden Tags
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Solution Overview
Problem
Existing security management of instructions in a CPU's cache requires software-level operations, which are inefficient and delay the authentication process, especially during a cache miss.
Innovation Solution
An apparatus and method for performing authenticated encryption with associated data (AEAD) operation using a bus control circuit, block buffer, tag buffer, and AEAD circuit to authenticate encrypted instructions directly from memory without software involvement, allowing on-the-fly authentication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software level operations are used for security management of instructions, then authentication can be performed, but the process requires more setting operations and delays the authentication process
Solution Approach 1:
The patent replaces software-level authentication operations with a hardware-based AEAD circuit that performs authenticated encryption with associated data. The circuit includes an encryption unit for encrypting instructions, an authentication unit for generating authentication tags, and a comparison unit for verifying tags, all operating in parallel hardware architecture to eliminate software processing delays
Solution Approach 2:
The patent pre-computes and stores authentication tags (golden tags) alongside encrypted instructions in the cache memory during system initialization or instruction storage. When authentication is needed, the hardware circuit simply retrieves and compares the pre-computed tags without performing complex cryptographic operations during execution, enabling on-the-fly authentication
2Productivity
If hardware-based authentication is implemented, then authentication can be performed without software involvement, but additional hardware components are required
Solution Approach 1:
The patent merges the encryption function, authentication tag generation function, and tag comparison function into a single integrated AEAD circuit module. The circuit shares common resources such as the cache memory for storing both encrypted instructions and golden tags, and uses unified control logic to coordinate authentication operations, thereby reducing overall hardware complexity
Solution Approach 2:
The AEAD circuit is designed as a universal authentication module that can handle multiple instruction types and encryption operations through a single hardware structure. The circuit accepts encrypted instructions from the cache, performs AEAD operations, and outputs authenticated instructions, serving multiple security functions within one integrated unit
Data Source
AI summary
An apparatus and a method for performing an authenticated encryption with associated data (AEAD) operation of an encrypted instruction and a golden tag stored in a memory device in an event of a cache miss are provided. The apparatus includes a bus control circuit, a block buffer, a tag buffer and an AEAD circuit. The bus control circuit receives a read address from a cache for reading the encrypted instruction and the golden tag from the memory device. The block buffer receives and stores the encrypted instruction from the bus control circuit, wherein a size of the block buffer is preset to be N times a size of one cache line. The tag buffer receives and stores the golden tag from the bus control circuit. The AEAD circuit performs the AEAD operation upon the encrypted instruction and the golden tag to check whether the encrypted instruction is tampered or not.