Acoustic Echo Cancellation Clock Synchronization via Two-Stage Resampling

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Solution Overview

Problem

Conventional acoustic echo cancellers struggle with clock synchronization between speakers and microphones connected over digital links, leading to inadequate echo cancellation due to differing sampling clocks, which causes phase drift and hinders adaptive filter convergence.

Innovation Solution

A two-stage clock synchronization approach is implemented, combining hardware and software methods to estimate and adjust clock differences, first with coarse synchronization in hardware and then fine synchronization using a re-sampler, allowing for effective synchronization without knowledge of hardware clock information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If speakers and microphones are connected over digital links with different sampling clocks, then system flexibility and adaptability are improved, but clock synchronization deteriorates causing phase drift and inadequate echo cancellation

Engineering Contradiction:
Improvesystem flexibilityVSAvoidclock synchronization
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent divides clock synchronization into two distinct stages: coarse synchronization using hardware methods to handle large frequency offsets, and fine synchronization using software resampling to correct residual phase differences. This segmentation allows each stage to optimize for its specific requirements, achieving reliable synchronization while maintaining system flexibility with different sampling clocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary synchronization mechanism that operates between the speaker and microphone sampling clocks. This intermediary system estimates clock differences by analyzing signal characteristics and applies correction through hardware and software components, enabling reliable echo cancellation despite independent clock sources.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If hardware clock synchronization is used, then synchronization speed is improved, but flexibility to handle different clock configurations deteriorates

Engineering Contradiction:
Improvesynchronization speedVSAvoidclock configuration flexibility
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent segments the synchronization process into coarse hardware synchronization for rapid initial alignment and fine software synchronization for precise adjustment. This allows the system to achieve fast synchronization response while maintaining flexibility to handle various clock configurations through the software stage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic synchronization where the system can adaptively switch between hardware and software methods based on the detected clock difference magnitude. The synchronization mechanism dynamically adjusts its operation mode to optimize both speed and flexibility for different clock configuration scenarios.

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If software resampling is used for fine synchronization, then synchronization precision is improved, but processing complexity and time consumption increase

Engineering Contradiction:
Improvesynchronization precisionVSAvoidprocessing complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the synchronization task by performing the computationally intensive fine synchronization only after coarse synchronization has reduced the frequency offset. This segmentation limits the processing complexity to only the necessary fine adjustment phase, achieving high precision while minimizing overall computational burden.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary coarse synchronization using hardware methods before implementing fine synchronization through software resampling. This preliminary action reduces the complexity required for the subsequent software processing by pre-aligning the clocks, thereby achieving high precision with reduced overall processing complexity.

Inventive Principle:
Principle #10Preliminary action

4Reliability

If adaptive filters are used for echo cancellation, then echo removal performance is improved, but convergence speed deteriorates due to phase drift from clock differences

Engineering Contradiction:
Improveecho cancellation performanceVSAvoidfilter convergence speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements feedback mechanisms in both stages of synchronization. The coarse synchronization uses feedback from frequency offset detection to adjust hardware clocks, while the fine synchronization uses feedback from phase difference measurement to adjust software resampling parameters. This feedback ensures rapid convergence of adaptive filters by continuously correcting phase drift.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent performs preliminary clock synchronization before adaptive filter operation begins. By pre-aligning the sampling clocks through coarse and fine synchronization stages, the system eliminates phase drift that would otherwise hinder adaptive filter convergence, thereby achieving both rapid convergence and high echo cancellation performance.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9025762B2System and method for clock synchronization of acoustic echo canceller (AEC) with different sampling clocks for speakers and microphones
Publication Date: 2015.05.05 CISCO TECHNOLOGY INC
  • US9025762B2 patent drawing
  • US9025762B2 patent drawing
  • US9025762B2 patent drawing

AI summary

Clock synchronization for an acoustic echo canceller (AEC) with a speaker and a microphone connected over a digital link may be provided. A clock difference may be estimated by analyzing the speaker signal and the microphone signal in the digital domain. The clock synchronization may be combined in both hardware and software. This synchronization may be performed in two stages, first with coarse synchronization in hardware, then fine synchronization in software with, for example, a re-sampler.