AES-256 Encryption Circuit with Time-Shared Pipeline
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Solution Overview
Problem
The implementation of AES-256 encryption in computing systems inherently has a higher overhead compared to AES-128, and high-volume data-driven AI applications require enhanced bandwidth in secure communications, necessitating more efficient approaches to support post-quantum encryption standards.
Innovation Solution
A time-shared round data path with a depth-2 pipeline is implemented, allowing for atomic execution of two 14-round AES-256 encryption operations in 30 cycles at a high-frequency clock speed, reducing latency and increasing throughput, while maintaining high clock speeds up to 4.5 GHz on 10nm processing cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If AES-256 encryption is implemented in computing systems, then security against quantum attacks is improved, but overhead increases by approximately 40% compared to AES-128
Solution Approach 1:
The AES-256 encryption process is divided into multiple 14-round segments that can be executed in parallel. The circuit is segmented into separate round execution units, each handling a specific portion of the encryption rounds, allowing concurrent processing of multiple encryption operations simultaneously.
Solution Approach 2:
Multiple AES-256 encryption operations are merged into a single unified circuit that processes two independent encryptions concurrently. The circuit combines key expansion units, round function units, and state transformation units to handle multiple plaintexts through the same cryptographic algorithm in parallel.
2Reliability
If traditional AES-256 implementation is used, then security is improved, but bandwidth efficiency deteriorates due to higher overhead
Solution Approach 1:
The encryption circuit maintains continuous operation by pipelining multiple encryption operations. While one encryption is being processed through the round function, another is simultaneously undergoing key expansion, ensuring that the circuit operates at full capacity without idle cycles and maximizes throughput.
Solution Approach 2:
The circuit dynamically allocates resources between different encryption operations based on input availability. The key expansion and round function units can switch between processing different plaintexts in sequence, optimizing resource utilization and maintaining high throughput for varying workloads.
3Reliability
If AES-256 encryption is implemented with high security requirements, then reliability is improved, but processing speed deteriorates due to increased complexity
Solution Approach 1:
The 14 rounds of AES-256 are segmented into multiple independent execution units, each capable of processing a subset of rounds. This segmentation allows the circuit to pipeline operations so that while one unit completes its rounds, another unit is already processing the next encryption, maintaining high speed despite the increased number of rounds required for AES-256.
Data Source
AI summary
Techniques for implementing Advanced Encryption Standard (AES)-256 encryption. An implementation includes a time-shared round data path with a depth-2 pipeline that results in an atomic execution of two 14-round AES-256 encryption operations in 30 cycles while operating at the same high-frequency clock used for processing cores of a computing system. The technology described herein uses only two cycles of latency per round while supporting a very high maximum operating clock speed.