AES Arithmetic Circuit Downsizing via System Memory Reuse
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Solution Overview
Problem
Conventional techniques are insufficient for downsizing AES arithmetic circuits, particularly when they are embedded in electronic devices, as they do not consider the reuse of existing memory devices within the system for AES processing, leading to unnecessary additional memory requirements.
Innovation Solution
The proposed solution involves diverting a system's memory device, such as a communication buffer or RAM, to be used for AES arithmetic processing, eliminating the need for a separate memory device within the AES arithmetic circuit, and utilizing a minimal set of circuits for arithmetic processing, including an ALU with XTIME, SBOX, and XOR functions, to perform AES encryption with only five basic instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a separate memory device is added to the AES arithmetic circuit, then encryption processing capability is improved, but device size and complexity increase
Solution Approach 1:
The patent makes the system's existing memory device serve dual purposes: its original communication buffer function and AES arithmetic processing function. By controlling the memory device to store and retrieve data according to specific address generation rules during AES operations, the same physical memory hardware performs both its traditional role and encryption-related data storage, thereby eliminating the need for a separate dedicated memory component in the AES circuit.
2Device complexity
If conventional AES circuit design is used, then encryption functionality is achieved, but further downsizing is insufficient
Solution Approach 1:
The patent extracts the memory function from the AES arithmetic circuit design and relocates it to the system's existing memory device. By removing the dedicated memory component from the AES circuit and utilizing external memory resources instead, the patent achieves significant circuit size reduction while maintaining complete AES encryption functionality through proper address management and data flow control.
Solution Approach 2:
The patent merges the AES arithmetic circuit with the system's existing memory device by establishing direct control relationships between the AES unit and memory address generation. Instead of maintaining separate memory hardware, the AES circuit integrates with the system memory through coordinated address generation and data transfer protocols, combining multiple functions into a unified resource architecture.
Data Source
AI summary
According to an embodiment, an arithmetic device includes an arithmetic processing unit, an address generating unit, and a control unit. The arithmetic processing unit performs a plurality of arithmetic processing used in an encryption method. Based on an upper bit of the address of the first piece of data and based on an offset which is a value corresponding to a counter value and which is based on the address of the first piece of data, the address generating unit generates addresses of the memory device. The control unit controls the arithmetic processing unit in such a way that the arithmetic processing is done in a sequence determined in the encryption method, and that specifies an update of the counter value at a timing of modifying the type of data and at a timing of modifying data.