AES Encryption Circuit Optimizing Clock Cycle Balance
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Solution Overview
Problem
Current AES encryption/decryption processes are limited by high clock cycle requirements, which hinder the achievement of high-speed data transmission necessary for secure communication, especially in high-data-volume applications like video distribution, as they require significant processing time and resources.
Innovation Solution
The proposed AES encryption/decryption circuit optimizes signal processing by minimizing the difference in summation of signal processing time across clock cycles, allowing for a reduction in the number of cycles required for encryption and decryption, thereby enhancing processing speed without increasing individual sub-block transformation times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional AES implementation methods are used with one round function executed per clock cycle, then the circuit complexity is manageable, but the processing speed is insufficient for high-speed encryption communication
Solution Approach 1:
The AES encryption/decryption process is segmented into distinct functional units (SubBytes unit, ShiftRows unit, MixColumns unit, AddRoundKey unit) that can operate in parallel. Each unit handles a specific transformation, allowing multiple operations to be performed simultaneously within a single clock cycle, thereby increasing processing speed without proportionally increasing overall circuit complexity.
Solution Approach 2:
The circuit design implements a unified AES core that can perform both encryption and decryption operations using the same structural framework. By configuring the same functional units with different control signals and round key schedules, the circuit achieves multi-functionality, reducing the need for separate encryption and decryption circuits and thus managing complexity while maintaining high speed.
2Productivity
If multiple round functions are executed within one clock cycle, then processing speed increases, but the signal processing time distribution becomes unbalanced across clock cycles
Solution Approach 1:
The circuit employs dynamic control mechanisms that adjust the operation of each functional unit based on the current clock cycle phase. Control signals dynamically enable or disable specific transformations (SubBytes, ShiftRows, MixColumns, AddRoundKey) in each round, allowing the circuit to execute multiple rounds per clock cycle while maintaining balanced time distribution through adaptive scheduling.
Solution Approach 2:
The design ensures continuous utilization of all functional units across clock cycles by pipelining the AES operations. While one round is being processed in the SubBytes unit, the ShiftRows unit is already preparing the next round's input, and the MixColumns unit is processing previous data. This continuous action eliminates idle time and balances the workload across clock cycles, increasing productivity without creating time imbalances.
Data Source
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AI summary
This invention makes the number of cycles required for AES encryption or decryption by hardware smaller than before by reducing the difference among the summation of the signal processing time for each sub-block transformations in each clock cycle period. To do this, an encryption/decryption circuit includes a first AddRoundKey Transformation module, a second AddRoundKey Transformation module, a ShiftRows Transformation module, a SubBytes Transformation module, a MixColumns Transformation module, and a data holding unit, wherein in a cycle of encryption, the first AddRoundKey Transformation module and the second AddRoundKey Transformation module are executed using different Round Keys.