AES Encryption Processor Clock Gating Power Reduction
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Solution Overview
Problem
Existing AES processors for battery-powered wireless devices face challenges in achieving energy efficiency and reducing power consumption, particularly in low-cost systems that require low peak power and area-efficient security implementations.
Innovation Solution
The proposed encryption processor incorporates a byte permutation unit with clock gating circuitry, reducing the number of active registers and logic circuitry, and utilizes a pipelined architecture with a MixColumns unit and key expansion unit optimized for minimal chip area and power consumption, allowing for efficient processing of AES-128 encryption standard.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If clock gating circuitry is introduced to reduce register activity, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The clock gating circuitry implements periodic action by selectively enabling clock signals to registers based on operational requirements. The clock gate signal is periodically activated only when register updates are needed, rather than continuously clocking all registers. This reduces power consumption by approximately 60% while managing the added complexity through systematic control rather than continuous operation.
2Area of stationary object
If data path width is reduced to 8 bits for area efficiency, then chip area is reduced, but processing throughput decreases
Solution Approach 1:
The AES processing algorithm is segmented into multiple stages with 8-bit data path width, where each stage processes one byte at a time through sequential operations. The byte permutation unit, MixColumns unit, and key expansion unit are divided into modular components that can be activated independently. This segmentation allows the system to maintain small chip area while achieving acceptable throughput by processing data in manageable chunks rather than requiring wide parallel paths.
Solution Approach 2:
The key expansion unit performs preliminary action by pre-computing and storing round keys in a compact format before they are needed for encryption operations. This allows the main encryption process to proceed efficiently without requiring large real-time key storage areas. The preliminary key generation and storage optimization enables the system to maintain small chip area while preserving encryption throughput.
Data Source
AI summary
An Encryption processor is disclosed comprising an S-box unit, a byte permutation unit, a MixColumns unit and a key expansion unit. In an embodiment the byte permutation unit comprises a data input terminal for receiving input data, two or more row processors, each row processor having an input coupled to the input terminal and an output, and a clock gating circuit for generating for each of the two or more row processors a gated clock signal. Furthermore, a clock gated key expansion unit is disclosed. By clock gating, the power consumption of the processor is reduced which extends the battery life time in battery powered devices.