AES Core With Independent Input Output Timing
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Solution Overview
Problem
Existing hardware implementations of the Advanced Encryption Standard (AES) algorithm face inflexibility due to restrictive interface timing, making them difficult to use and often resulting in larger systems compared to discrete cores for individual encryption operations.
Innovation Solution
A hardware core architecture that uses a single key round generator to dynamically assign round keys and allows independent input and output times, enabling flexible interface timing and supporting staggered or delayed plaintext blocks without predictability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pipelining and unrolling are used to speed up AES processing, then processing speed is improved, but interface timing becomes restrictive and inflexible
Solution Approach 1:
The patent segments the AES processing into multiple independent pipeline stages (key generation stage, state transformation stages, etc.), where each stage can operate independently. This segmentation allows the interface timing to be flexible while maintaining high processing speed through parallel execution of stages.
Solution Approach 2:
The patent implements dynamic control of the pipeline stages, where the timing and execution of each stage can be adjusted independently based on input availability. This dynamic approach allows the system to maintain high speed processing while adapting to variable interface timing requirements.
2Device complexity
If fixed interface timing is used in hardware AES core, then routing and area are optimized, but the system becomes difficult to use and may require larger system size
Solution Approach 1:
The patent creates a universal AES core architecture that can handle multiple timing scenarios and input patterns through a single design. The configurable pipeline stages and dynamic control logic allow the same hardware core to adapt to different timing requirements, improving usability without increasing routing complexity.
3Adaptability or versatility
If discrete hardware cores are used for each encryption operation, then interface timing flexibility is improved, but system size increases
Solution Approach 1:
The patent merges multiple encryption operations into a single hardware core through pipelining, where different stages of the encryption process for multiple blocks are executed simultaneously in parallel pipeline stages. This consolidation maintains timing flexibility while reducing the total system area compared to using separate discrete cores.
Data Source
AI summary
Encrypting data using the Advanced Encryption Standard (AES) algorithm uses pipelined registers to perform the AES processing. Any number of registers (two or more) each holds a block of plaintext data. A multiplexer accepts one block of data at a time and feeds it into the pipeline processing unit. The processing unit performs a round of encryption upon the block. A key round generator generates a set of round keys for the pipeline processing unit using a cipher key and the set of round keys are stored in parallel in memory devices, each memory device corresponding to one of the registers. The pipeline processing unit receives the correct round key for each round of encryption from the memory device corresponding to the block of data being encrypted by the add round key unit at that time. A read counter (one per register) indexes one of the round keys in the appropriate memory device thus enabling the indexed round key to be input to the pipeline processing unit for the appropriate round and block.