Pipelined AES-GCM Engine for High-Throughput TLS Encryption
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Cloud computing environments face challenges in achieving high-throughput AES-GCM encryption/decryption with millions of different secret keys while maintaining confidentiality and integrity, especially under the threat of quantum attacks, due to latency overhead from pre-computing authentication keys and fixed input block sizes.
Innovation Solution
A pipelined architecture for a post-quantum AES-GCM engine that computes authentication keys on the fly for every input data-block, supports variable input block sizes through automatic padding, and enables zero-delay context switching among multiple connections by deriving authentication keys from encryption keys, allowing for real-time processing of TLS packets with variable payload sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If authentication keys are pre-computed for every connection, then authentication speed is improved, but latency overhead increases and device complexity increases
Solution Approach 1:
The patent pre-computes authentication keys (h, h2, h3, h4) during the TLS handshake phase and stores them in lookup tables. This preliminary action allows the authentication tag computation to proceed rapidly during data encryption without real-time key generation delays, thus improving authentication speed while minimizing latency overhead through efficient pre-computation and storage.
2Device complexity
If fixed input block sizes are used, then processing simplicity is improved, but adaptability deteriorates
Solution Approach 1:
The patent implements a dynamic input block sizing mechanism that automatically adjusts the block size based on the actual data payload length. The system divides variable-length input data into appropriate blocks (e.g., 16-byte, 32-byte, 64-byte blocks) and processes them through the authentication pipeline, maintaining processing simplicity while achieving full adaptability to different input sizes through automated block segmentation.
3Productivity
If context switching between multiple connections is implemented, then productivity is improved, but latency overhead increases
Solution Approach 1:
The patent pre-computes and caches authentication keys (h, h2, h3, h4) during the TLS handshake phase before actual data transmission begins. This preliminary computation eliminates the need for real-time key generation during context switching between connections, enabling zero-latency connection establishment and allowing the system to rapidly switch between millions of concurrent connections without setup delays.
4Device complexity
If authentication keys are derived from encryption keys, then device complexity is reduced, but security requirements increase
Solution Approach 1:
The patent merges the authentication key derivation function with the encryption key by computing authentication keys (h, h2, h3, h4) directly from the encryption key using AES-256 operations. This consolidation eliminates separate key storage and management infrastructure, reducing device complexity while maintaining security through the cryptographic strength of AES-256 and the deterministic derivation process that ensures authentication keys remain secure.
Data Source
AI summary
An apparatus comprises an input register to receive a transport layer data packet, an encryption/decryption pipeline communicatively coupled to the input register, comprising a first section comprising a set of advanced encryption standard (AES) engines including at least a first AES engine to perform encryption and/or decryption operations on input data from the at least a portion of a transport layer data packet, a second AES engine to determine an authentication key, and a third AES engine to determine an authentication tag mask, a second section comprising a first set of Galois field multipliers comprising at least a first Galois field multiplier to compute a first multiple of the authentication key, a third section comprising a second set of Galois field multipliers to compute a first partial authentication tag, and a fourth section comprising a processing circuitry to compute a second partial authentication tag and a final authentication tag.