Processor Instruction Set Extension for AES Encryption
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The Advanced Encryption Standard (AES) algorithm is typically compute-intensive and often performed in software or special-purpose processors, limiting its widespread use for encrypting all information stored on computers, such as those on mobile devices, where encryption is needed to protect sensitive data.
Innovation Solution
An instruction set extension is implemented in a general-purpose processor to perform AES encryption and decryption, including an on-the-fly key scheduler and microoperations for AES rounds, allowing for efficient encryption and decryption of 128-bit blocks with key sizes of 128, 192, and 256 bits, and supporting customizable numbers of rounds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If AES encryption is performed in software or special-purpose processors, then encryption capability is achieved, but device complexity and processing overhead increase
Solution Approach 1:
The patent merges AES encryption functionality directly into the general-purpose processor's instruction set architecture by integrating execution units that can perform AES operations natively. This combines the security benefits of dedicated encryption hardware with the versatility of general-purpose processors, eliminating the need for separate software implementations or specialized hardware modules.
Solution Approach 2:
The execution unit is designed to perform multiple functions including AES encryption, decryption, and key scheduling operations within a single hardware component. This multi-functional approach allows the processor to handle various cryptographic operations without requiring separate dedicated circuits for each function, thereby reducing overall device complexity.
2Adaptability or versatility
If AES encryption is performed using traditional software implementation, then flexibility is maintained, but processing speed and efficiency decrease
Solution Approach 1:
The patent replaces the mechanical software-based encryption process with a hardware-based execution unit that operates at processor speeds. This substitution maintains the flexibility of software control while achieving the speed benefits of hardware implementation, as the execution unit can be invoked through standard instruction sequences.
3Reliability
If all information on mobile devices is encrypted, then security is enhanced, but memory requirements and computational overhead increase
Solution Approach 1:
The patent extracts the key scheduling functionality into a dedicated on-the-fly key scheduler component that operates independently from the main encryption/decryption execution unit. This extraction allows for efficient key management with reduced memory requirements, as keys are generated and managed on-demand rather than requiring large key schedules to be stored in memory.
Solution Approach 2:
The on-the-fly key scheduler implements self-service by automatically generating round keys from the master key during the encryption/decryption process without requiring external intervention or large pre-computed key schedules. This self-generating approach minimizes memory requirements while maintaining security.
Data Source
AI summary
A processor of an aspect is to perform a Single Instruction Multiple Data (SIMD) instruction. The SIMD instruction is to indicate a source register storing input data to be processed by a round of AES and is to indicate a source of a round key to be used for the round of AES. The processor is to perform the SIMD instruction to perform the round of AES on the input data using the round key and store a result of the round of AES in a destination. In one aspect, the SIMD instruction is to provide a parameter to specify whether or not a round of AES to be performed is a last round. Other instructions, processors, methods, and systems are described.