Flexible AES Instruction Set for General Purpose Processors
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Solution Overview
Problem
The Advanced Encryption Standard (AES) algorithm is compute-intensive and typically performed in software or special-purpose processors, limiting its use for encrypting all information stored on computers, especially on mobile devices, where flexibility and performance in key generation are required for applications like network packet processing and disk encryption.
Innovation Solution
A flexible architecture and instruction set for performing AES encryption and decryption in a general-purpose processor, allowing for on-the-fly key generation and separate execution ports for AES round key operations, enabling efficient encryption and decryption of data with varying key sizes and number of rounds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If AES algorithm is performed in software or special-purpose processors, then encryption and decryption can be achieved, but performance is limited and flexibility in key generation is reduced
Solution Approach 1:
The AES algorithm is divided into separate execution ports: one for AES round operations and another for key generation operations. This segmentation allows independent optimization of each function while maintaining overall system performance and flexibility.
Solution Approach 2:
The processor architecture implements dynamic key generation capabilities that can adapt to different key sizes (128, 192, or 256 bits) and numbers of rounds (10, 12, or 14) based on security requirements, allowing the system to flexibly adjust parameters without hardware reconfiguration.
2Device complexity
If AES algorithm is implemented with fixed architecture, then implementation is simpler, but adaptability to different key sizes and round numbers is limited
Solution Approach 1:
The processor design incorporates universal execution units that can handle multiple AES configurations (different key sizes and round numbers) through a single unified architecture, eliminating the need for multiple specialized hardware implementations.
Solution Approach 2:
The architecture allows dynamic modification of operational parameters including key size (128/192/256 bits) and number of rounds (10/12/14) through software-controlled configuration, enabling the same hardware to adapt to different security requirements without physical reconfiguration.
3Device complexity
If dependent instructions are used for key generation, then instruction execution is simpler, but performance is reduced due to sequential execution requirements
Solution Approach 1:
The processor separates key generation instructions from AES round instructions into different execution ports, allowing them to execute independently and in parallel rather than sequentially, thereby improving performance without increasing instruction complexity.
Solution Approach 2:
By enabling parallel execution of key generation and AES round operations through separate execution ports, the system maintains continuous productive work without idle waiting periods, maximizing throughput and encryption performance.
Data Source
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AI summary
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a "one round" pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.