Processor Instructions for AES Encryption and Decryption

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Solution Overview

Problem

Current software-based encryption and decryption processes, such as those using the AES algorithm, suffer from performance limitations due to the lack of native support for Galois Field arithmetic in off-the-shelf x86 CPUs, leading to processing power inefficiencies and potential utility limitations.

Innovation Solution

A processor-based system that performs encryption and decryption through a series of rounds, utilizing instructions like PSBOX and PRCMIXB to execute transformations in parallel, including AddRoundKey, SubBytes, ShiftRows, and MixColumns operations, optimized for hardware execution to enhance performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If encryption/decryption is implemented in software on off-the-shelf x86 CPUs, then flexibility and compatibility are maintained, but performance is severely limited due to lack of native Galois Field arithmetic support

Engineering Contradiction:

Improveencryption/decryption speedVSAvoidprocessing power requirements

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces software-based encryption/decryption operations with dedicated hardware circuitry that natively performs Galois Field arithmetic. The encryption/decryption device includes specialized units for executing AES operations in hardware, eliminating the need for software interpretation and complex CPU processing, thereby achieving significant performance improvement while reducing overall processing power requirements.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the operational parameters by implementing parallel processing capabilities and optimizing the hardware architecture to handle multiple encryption/decryption operations simultaneously. The device uses parallel execution units and optimized data paths to process multiple blocks of data in parallel, fundamentally changing the performance characteristics from sequential software processing to parallel hardware processing.

Inventive Principle:

Principle #35Parameter changes

2Ease of operation

If software-based AES encryption is used, then implementation flexibility is maintained, but processing power consumption increases significantly

Engineering Contradiction:

Improveimplementation flexibilityVSAvoidprocessing power consumption

Core Design Contradiction:

Ease of operationVSUse of energy by moving object

Solution Approach 1:

The patent substitutes software-based AES implementation with dedicated hardware encryption/decryption units that are optimized for Galois Field arithmetic operations. This hardware implementation performs the same encryption/decryption functions with significantly lower power consumption by using specialized circuits instead of general-purpose CPU instructions, thereby reducing processing power requirements while maintaining implementation flexibility through programmable control.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS8280040B2Processor instructions for improved AES encryption and decryption

Publication Date: 2012.10.02 MEDIATEK INC

AI summary

Encrypting information involving the execution of a first instruction and a second instruction on a processor. The first instruction causes the processor to perform an AddRoundKey transformation followed by a ShiftRows transformation. The second instruction causes the processor to perform a ShiftRows transformation followed by a MixColumns transformation. These instructions are useful for performing AES encryption. The first and second instructions also have inverse modes that may be used to perform AES decryption.