Processor AES Unit Cycle-by-Cycle Throughput
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Solution Overview
Problem
Prior processor architectures for implementing the Advanced Encryption Standard (AES) instructions require multiple cycles of throughput, resulting in reduced performance due to lack of full pipelining, leading to inefficiencies in data encryption and decryption processes.
Innovation Solution
The proposed solution involves shifting a received data word and processing it using a substitution transformation in the first cycle, followed by a mixed column transformation and addition of a round key in the next cycle, achieving cycle-by-cycle throughput for encoding and decoding operations within an AES unit of a processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If prior processor architectures are used to implement AES instructions, then the implementation is simpler to design, but the throughput is reduced to multiple cycles per instruction
Solution Approach 1:
The AES encryption process is divided into distinct operational stages (substitution transformation, mixed column transformation, key addition) that can be executed in separate pipeline cycles. Each stage is implemented as a separate functional unit that processes data independently, enabling parallel execution across multiple cycles while maintaining single-cycle throughput for each instruction.
Solution Approach 2:
The processor architecture implements dynamic pipelining where multiple instruction stages are overlapped in time. The substitution unit, mixed column unit, and key addition unit operate concurrently in different pipeline stages, allowing the system to adapt its execution flow dynamically while achieving single-cycle instruction completion.
2Productivity
If full pipelining is implemented for AES operations, then single-cycle throughput is achieved, but the microarchitecture complexity increases
Solution Approach 1:
The pipelined AES processor is segmented into specialized functional units (substitution transformation unit, mixed column transformation unit, key addition unit) that each handle specific operations. This segmentation allows complex AES operations to be distributed across multiple simple, dedicated units operating in parallel pipeline stages, reducing the complexity burden on any single unit while achieving single-cycle throughput.
3Use of energy by moving object
If multiple cycles are used per AES instruction, then the processor design is simpler, but power efficiency is reduced
Solution Approach 1:
The processor employs dynamic pipelining where functional units are activated and deactivated based on the current instruction stage. This dynamic operation allows the processor to complete AES instructions in a single cycle by coordinating multiple units, improving power efficiency compared to multi-cycle execution while managing complexity through controlled activation of pipeline stages.
Data Source
AI summary
Methods and apparatus are provided for implementing the advanced encryption standard. The apparatus comprises a first multiplexer receiving during a first cycle a data word, a substitution transformation of the data word and inverse substitution transformation of the data word to provide a first output. During the next cycle, a second multiplexer receives the first output, a mixed column transformation of the first output and an inverse mixed column transformation of the first output to provide a second output. Also in the next cycle, the second output is added to a round key to provide one round of an encoded or decoded digital word compliant with the advanced encryption standard with cycle-by-cycle throughput. The method comprises shifting a received data word and processing the shifted data word using a substitution transformation (encoding) or an inverse substitution transformation (decoding) during a first cycle in an advanced encryption standard unit of a processor. In the next cycle, the result from the first cycle is processed using a mixed column transformation (encoding) or an inverse mixed column transformation (decoding) and the result is added to a round key to provide one round compliant with the advanced encryption with cycle-by-cycle throughput.