AES Processor Architecture with Shared Operators and Random Masking
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Solution Overview
Problem
Conventional AES-type algorithms are bulky in terms of hardware architecture and memory usage, and are susceptible to differential power analysis attacks, which compromise their security.
Innovation Solution
A processor architecture that executes AES-type algorithms using a shared group of hardware operators, reduces memory size by nested operation execution, and incorporates random masking to counter differential power analysis attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional AES-type algorithms are implemented using separate hardware operators for each operation, then the algorithm execution is straightforward and reliable, but the hardware architecture becomes bulky and memory usage increases
Solution Approach 1:
The patent merges multiple separate hardware operators (substitution box, circular permutation, XOR combination) into a shared group of operators that can be reused across multiple rounds. This consolidation reduces the overall hardware footprint and memory usage while maintaining the algorithm's functional integrity through proper state management and operator sharing mechanisms
Solution Approach 2:
The hardware operators are designed to be universal and multi-functional, capable of performing different operations (substitution, permutation, XOR combination) in different rounds. This multi-functionality allows the same hardware components to serve multiple purposes throughout the algorithm execution, reducing redundancy and hardware complexity
2Reliability
If standard AES execution is used without additional security measures, then the implementation is simple and fast, but it becomes susceptible to differential power analysis attacks
Solution Approach 1:
The patent introduces random masking values that dynamically change the operational parameters of the hardware operators during execution. By XORing intermediate results with random values, the power consumption profile becomes unpredictable and unrelated to the actual secret key operations, thereby resisting differential power analysis attacks while adding only minimal architectural complexity
Data Source
AI summary
A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comprises: a first input register (102) containing an input data block column; an output register (111) containing an output data block column or an intermediate block column; a second input register (101) containing a key block column or the intermediate data blocks; a block substitution element (104) receiving the data one block at a time following the selection (103) thereof in the first register and providing, for each block, a column of blocks; an element (109) applying a cyclic permutation to the substitution circuit column blocks; and an Exclusive-OR combination element (110) combining the permutation circuit column blocks with the content of the second register, the result of said combination being loaded into the output register.