AES S-Box Using Variable LFSR Seeds for Side-Channel Resilience
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Solution Overview
Problem
AES cryptographic systems are vulnerable to side-channel attacks, particularly due to side-channel leakage from the S-box operation during encryption, which can reveal the secret key.
Innovation Solution
The implementation of an AES cryptographic system using two forward-reverse linear-feedback shift registers (LFSRs) pairs for the S-box, with different initialization seeds for each pair, to perform multiplicative inversion and reduce side-channel leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional S-box implementation is used in AES, then the encryption function is achieved, but side-channel leakage occurs that reveals secret key information
Solution Approach 1:
The patent changes the initialization seed parameter of the LFSR from a fixed value to a variable value that changes with each encryption operation. This parameter change causes the S-box computation to complete in variable time, preventing correlation between fixed-time power consumption patterns and secret key data, thereby eliminating side-channel leakage
Solution Approach 2:
The patent introduces dynamic behavior to the S-box implementation by using variable initialization seeds that cause the LFSR to execute for different numbers of clock cycles. This dynamic execution time prevents attackers from using fixed-time correlation analysis, as the timing relationship between secret key operations and power consumption measurements becomes unpredictable
2Device complexity
If LFSR-based S-box with fixed initialization seed is used, then hardware complexity is reduced, but side-channel vulnerability remains due to fixed execution time
Solution Approach 1:
The patent maintains the simple LFSR hardware structure but changes the initialization seed parameter from fixed to variable. This allows the system to achieve variable execution time and side-channel resistance without increasing hardware complexity, as the same LFSR circuit can operate with different seed values
3Reliability
If variable initialization seeds are used in LFSR pairs, then side-channel attack resilience is enhanced, but computation latency varies
Solution Approach 1:
The patent converts the harmful variable latency into a beneficial security feature. The variable execution time, which could be seen as a performance drawback, actually prevents side-channel attacks by ensuring that power consumption patterns cannot be correlated with secret key data through timing analysis. The harm of variable time is transformed into the benefit of enhanced security
Data Source
AI summary
An Advanced Encryption Standard (AES) cryptographic system and a method of performing Advanced Encryption Standard (AES) cryptography. The method comprises the steps of performing multiplicative inversion for SubBytes transformation using two forward-reverse linear-feedback shift registers, LFSRs, pairs; and using different respective initialization seeds for the pairs of forward-reverse LFSRs.