Ultra-Low Latency AES S-Box Logic Optimization
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Solution Overview
Problem
Traditional AES implementations suffer from high latency due to complex S-box transformations, which hinder efficient encryption and decryption processes, especially in high-performance microprocessors.
Innovation Solution
The implementation of ultra-low latency AES using a maximal prime coverage search algorithm and a divide-and-conquer substitute search algorithm to optimize the S-box logic, reducing the critical path latency to 9 NAND levels and 3 XOR levels, while maintaining processing throughput and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional AES S-box transformations are implemented, then encryption and decryption functionality is achieved, but latency is high
Solution Approach 1:
The patent segments the S-box transformation into multiple parallel computation paths, dividing the complex substitution operation into smaller manageable stages that can be executed concurrently, thereby reducing overall latency while maintaining functional correctness
Solution Approach 2:
The patent transforms the traditional sequential S-box computation into a parallel architecture by introducing additional computational dimensions, using multiple computation paths that operate simultaneously to reduce the critical path delay from traditional sequential execution
2Productivity
If S-box logic is optimized to reduce latency, then encryption speed improves, but area cost increases
Solution Approach 1:
The patent merges the S-box substitution logic with the MixColumns multiplication operation into a unified computational structure, eliminating redundant intermediate storage and computation stages, thereby achieving area efficiency while maintaining the optimized parallel throughput
Solution Approach 2:
The patent designs multi-functional computation units that perform both S-box substitution and MixColumns multiplication operations, allowing the same hardware resources to serve multiple cryptographic functions, thus reducing overall area cost while maintaining high processing throughput
Data Source
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AI summary
In one example, an apparatus for Advanced Encryption Standard (AES) substitutions box (S-box) encryption includes an S-Box logic function and a MixColumns multiplication operation. The S-box logic function takes as input a state and is an 8-bit to 8-bit logic function, and wherein the S-box logic function is minimized such that an S-box round comprises nine not-and (NAND) levels and duplications of a logical product of the minimized S-box logic function are eliminated. The MixColumns multiplication operation comprises a plurality of factors that are exclusive ORed (XOR) with an output of the S-box round to obtain a scaled 16-byte output.