Shared Logic AES Encryption Module for Mobile Systems
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Solution Overview
Problem
Conventional AES block algorithm implementations in mobile communication systems lack hardware usage flexibility and are not programmable, leading to inadequate security performance due to separate hardware modules for each mode of operation.
Innovation Solution
An encryption apparatus with a shared logic module that detects the current AES mode and uses shared hardware to perform encryption/decryption, along with a key controller to generate keys for different AES modes, allowing for flexible hardware usage and software implementation of the AES block algorithm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate hardware modules are used for each AES mode (AES_CMAC, AES_CTR, AES_CCM), then each mode can be implemented with dedicated hardware, but hardware usage flexibility is reduced and device complexity increases
Solution Approach 1:
The patent implements a universal AES hardware module that can perform multiple AES modes (AES_CMAC, AES_CTR, AES_CCM) through a single integrated structure. The module uses mode selection signals to configure the same hardware resources for different operational modes, eliminating the need for separate dedicated hardware modules for each mode while maintaining security performance.
Solution Approach 2:
The patent combines multiple separate AES mode implementation modules into a single integrated hardware module. By merging the functional blocks for AES_CMAC, AES_CTR, and AES_CCM into one unified structure with shared resources and a common control unit, the patent reduces device complexity and improves hardware flexibility while preserving the security capabilities of each individual mode.
2Reliability
If AES block algorithm is implemented with separate hardware modules for each process, then hardware security is provided, but the system is not programmable and adaptability is reduced
Solution Approach 1:
The patent introduces dynamic configurability to the AES hardware module through mode selection signals and control logic. The module can be dynamically reconfigured to operate in different AES modes (CMAC, CTR, CCM) based on input signals, transforming a static hardware implementation into a dynamic, adaptable system that maintains hardware security while gaining programmability and flexibility.
Solution Approach 2:
The patent introduces a control unit and mode selection logic as intermediary components between the input data and the AES processing blocks. This intermediary layer enables programmable control over which AES mode is executed by interpreting mode selection signals and configuring the appropriate processing path, thereby adding software-like programmability to the hardware implementation without compromising security.
3Adaptability or versatility
If multiple AES modes are supported with dedicated hardware modules, then comprehensive encryption capabilities are provided, but device complexity and hardware resource consumption increase
Solution Approach 1:
The patent designs a single AES hardware module with multi-functional capabilities that can execute AES_CMAC, AES_CTR, and AES_CCM modes. By making the hardware universal rather than mode-specific, the patent supports comprehensive encryption capabilities while reducing the number of hardware modules from three separate implementations to one integrated module, thereby reducing device complexity.
Solution Approach 2:
The patent merges the functional blocks, processing logic, and resources required for AES_CMAC, AES_CTR, and AES_CCM modes into a single consolidated hardware module. This consolidation eliminates redundant components and shared resources that would exist if separate modules were used, directly reducing device complexity and hardware resource consumption while maintaining support for all three AES modes.
Data Source
AI summary
A method and apparatus for improving hardware flexibility for encrypting data based on the Advanced Encryption Standard (AES) block algorithm is provided. An encryption apparatus is equipped with a shared logic including a mode detector which detects a current AES mode performed by an AES block algorithm, a shared hardware for use in the detected AES mode, and a key controller which generates a key for performing encryption/decryption in the AES mode.