AES ShiftRow Multiplexer Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current implementations of the 128-bit AES Algorithm face challenges in achieving optimal power consumption and area efficiency, particularly in portable devices and IoT applications where battery power is limited, due to the lack of effective power optimization techniques beyond traditional low-power VLSI methods.
Innovation Solution
The proposed solution involves modifying the AES algorithm by substituting or eliminating certain elements from its layers, utilizing multiplexers for the ShiftRow operation instead of registers, and implementing clock gating to achieve power optimization and area efficiency, thereby reducing unnecessary circuitry and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If traditional low-power VLSI techniques are applied to existing AES design, then power consumption is reduced to some extent, but area efficiency and power optimization are not sufficiently improved
Solution Approach 1:
The patent extracts and eliminates unnecessary circuitry from the AES design by modifying the algorithm structure. Specifically, certain elements from the AES layers are removed or substituted, resulting in a streamlined implementation that consumes less power and occupies smaller area while maintaining encryption functionality.
Solution Approach 2:
The patent changes the computational parameters of the AES algorithm by substituting traditional operations with optimized alternatives. The modified algorithm uses different computational approaches in various layers that reduce both power consumption and hardware area requirements compared to the standard AES implementation.
2Reliability
If registers are used to perform the ShiftRow operation in AES, then the operation is implemented correctly, but power consumption is higher
Solution Approach 1:
The patent substitutes the mechanical register-based shifting mechanism with a multiplexer-based selection mechanism. Instead of physically shifting bits through registers, the multiplexer selects and routes the appropriate data elements to their destination positions, achieving the same ShiftRow effect with lower power consumption.
Solution Approach 2:
The patent uses multiplexers to create selective data paths that copy and route data elements to their correct positions in the state matrix after substitution. The multiplexer outputs are copied to the appropriate locations in the new state matrix, eliminating the need for power-intensive register operations.
3Adaptability or versatility
If full AES algorithm layers are implemented, then complete encryption functionality is achieved, but area usage and power consumption increase
Solution Approach 1:
The patent extracts and removes redundant or less critical elements from the AES algorithm layers. By carefully selecting which elements to eliminate or substitute, the design maintains essential encryption functionality while reducing hardware area and power consumption suitable for resource-constrained devices.
Solution Approach 2:
The patent implements multi-functional circuitry that can perform multiple AES operations using shared hardware resources. The same circuit blocks are reused across different rounds and operations, reducing the overall area requirement while maintaining complete encryption functionality.
Data Source
AI summary
The present techniques may provide improved processing and functionality of performance of the 128-bit AES Algorithm, which may provide improved power consumption. For example, in an embodiment, an encryption and decryption apparatus may comprise memory storing a current state matrix of an encryption or decryption process and a plurality of multiplexers configured to receive from the memory current elements of the state matrix stored in the memory, perform a cyclic shift on the received elements of the state matrix, and transmit the shifted elements to the memory for storage as a new state matrix.