High-Speed AES–SM4 Cipher Circuit With Shared S-Box Logic
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Solution Overview
Problem
Existing solutions for implementing AES and SM4 ciphers require separate hardware accelerators, leading to increased product costs, silicon area, and leakage power, while software implementations fail to meet performance requirements.
Innovation Solution
A unified hardware accelerator is proposed that combines AES and SM4 ciphers using common S-box tables and shared affine transformation circuits, reducing circuit area and power overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate hardware accelerators are used for AES and SM4 ciphers, then each cipher can be implemented with dedicated optimization, but product cost, silicon area, and leakage power increase
Solution Approach 1:
The patent implements a unified hardware accelerator that can perform both AES and SM4 cipher operations using a single circuit structure. The design uses configurable control logic and parameter settings to switch between different cipher modes, eliminating the need for separate dedicated hardware accelerators for each cipher type while maintaining full functionality for both AES and SM4 operations
Solution Approach 2:
The patent combines the AES and SM4 cipher implementation into a single integrated hardware accelerator unit. By merging the control logic, data processing paths, and output interfaces into one unified structure, the design reduces silicon area and leakage power compared to having separate accelerators, while still providing dedicated optimization for both cipher types through configurable operation modes
2Reliability
If separate hardware accelerators are used for AES and SM4 ciphers, then each cipher can be implemented with dedicated optimization, but product cost increases
Solution Approach 1:
The unified hardware accelerator provides multi-cipher support through a single manufacturable unit, reducing bill of materials costs and assembly complexity. The design maintains dedicated optimization for both AES and SM4 ciphers through configurable control logic, achieving cost reduction without sacrificing implementation reliability
Solution Approach 2:
By merging AES and SM4 accelerator functions into one integrated circuit, the patent reduces manufacturing steps, testing requirements, and inventory complexity, thereby lowering overall product cost while maintaining the reliability benefits of dedicated hardware acceleration for both cipher types
3Reliability
If separate hardware accelerators are used for AES and SM4 ciphers, then each cipher can be implemented with dedicated optimization, but leakage power increases
Solution Approach 1:
The unified hardware accelerator implements both AES and SM4 ciphers in a single power domain, allowing shared power management resources and reduced overall leakage power. The design maintains dedicated optimization for each cipher through selective activation of specific circuit paths, achieving energy efficiency without compromising implementation reliability
Solution Approach 2:
By combining AES and SM4 accelerator circuits into one integrated unit, the patent reduces the total number of separate power domains, voltage regulators, and support infrastructure, thereby reducing cumulative leakage power while maintaining the reliability benefits of hardware-accelerated cipher operations
4Ease of manufacture
If software implementation is used for AES and SM4 ciphers, then hardware cost is reduced, but performance requirements are not met
Solution Approach 1:
The unified hardware accelerator provides high-performance cryptographic processing for both AES and SM4 ciphers through dedicated hardware circuits, meeting stringent performance requirements while avoiding the cost overhead of multiple separate accelerators. The design achieves this through shared control logic and configurable operation modes that enable fast cryptographic operations
5Area of stationary object
If a unified hardware accelerator is used for AES and SM4 ciphers, then silicon area and power overhead are reduced, but circuit complexity increases
Solution Approach 1:
The unified hardware accelerator is designed with modular segmentation, separating the cipher-specific processing logic from the shared control and data path infrastructure. This segmentation allows the complex unified design to be managed as distinct functional blocks, reducing design complexity while maintaining area efficiency through shared resources for both AES and SM4 operations
Data Source
AI summary
Disclosed embodiments relate to cipher accelerator circuit comprising: a first affine transformation circuit generating a first data block from an input data block, a SM4 S-box circuit configured to perform a first byte S-box operation according to a SM4 cipher and using a SM4 S-box table, the SM4 S-box operation being applied to the first transformed data block to obtain a substituted data block; and a second affine transformation circuit generating a second data block from the substituted data block, wherein the first and second affine transformation circuits are configured to perform multiplication of the substituted data block by a respective matrix and addition of a respective translation vector, and wherein the first and second affine transformations circuits are configured such that the second transformed data block is equal to the input data block processed by a second S-box operation according to another symmetric cipher using S-box tables.