AES State Array Control for Compact Low-Power Encryption
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Solution Overview
Problem
The increasing demand for miniaturized AES devices in IoT and mobile devices poses challenges due to constrained resources, requiring improved silicon area utilization and energy efficiency.
Innovation Solution
An AES device with a state array and key array of controllable data processing components, controlled by a control block module that instructs AES operations based on clock cycle count, utilizing shared circuitry and parallel processing to distribute operations over multiple cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If AES device is miniaturized for IoT and mobile devices, then device size is reduced, but silicon area utilization and energy efficiency become constrained
Solution Approach 1:
The AES device is segmented into distinct functional modules: state array for data storage, key array for key management, control block module for operation coordination, and functional block module for cryptographic operations. This segmentation allows each module to be optimized independently for area and power consumption while maintaining overall system efficiency.
Solution Approach 2:
The state array and key array are designed as multi-functional components that can serve multiple purposes within the AES architecture. The state array stores both plaintext/ciphertext data and intermediate transformation results, while the key array manages multiple round keys, reducing the need for separate dedicated storage structures and improving area utilization.
2Volume of moving object
If AES device is miniaturized for IoT and mobile devices, then device size is reduced, but silicon area utilization becomes constrained
Solution Approach 1:
The control block module and functional block module are merged into a tightly integrated control unit that coordinates all AES operations. This merging reduces the overhead of separate control structures and improves area utilization by sharing control logic and data pathways between different functional components.
Solution Approach 2:
The AES device utilizes a multi-dimensional array structure for state and key storage, transitioning from traditional linear storage to two-dimensional matrix organization. This dimensional change optimizes data access patterns and reduces the total area required for storage while maintaining cryptographic functionality.
3Measurement precision
If control block module instructs AES operations based on clock cycle count, then operation precision is improved, but device complexity increases
Solution Approach 1:
The control block module incorporates a clock cycle counter that automatically tracks and manages the progression of AES rounds without requiring external control signals. This self-service mechanism improves operation precision by ensuring accurate timing while reducing the complexity of external control circuitry.
Solution Approach 2:
The control block module uses feedback from the clock cycle counter to dynamically adjust control signals to the state array and key array. This feedback mechanism ensures precise synchronization of AES operations with the clock cycles while maintaining manageable device complexity through systematic control logic.
Data Source
AI summary
An Advanced Encryption Standard (AES) device and a computer-implemented method of performing an AES operation may be provided, the AES device comprising a state array of components comprising a first plurality of controllable data processing components, the first plurality of controllable data processing components including two or more controllable data processing state members that each include an additional input control and an additional input port; a key array of components comprising a second plurality of controllable data processing components; a control block module coupled to the state array of components and the key array of components, the control block module arranged to transmit one or more control signals to the state array of components and the key array of components; wherein the two or more controllable data processing state members are disposed at predetermined positions within the state array of components; and further wherein the control block module is arranged to instruct performance of one or more AES operations via usage of the additional input port of at least one of the two or more controllable data processing state members based on a clock cycle count.