AES Encryption SubBytes MixColumns Merging

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Solution Overview

Problem

There is a need for improved implementations of the Advanced Encryption Standard (AES) algorithm to enhance data encryption operations, particularly in terms of speed and efficiency to keep pace with increasing processing demands in modern computer systems.

Innovation Solution

The implementation of a novel encipher routine that combines the SubBytes and MixColumns transformations into a single operation, along with the ShiftRows and AddRoundKey transformations, optimizing the encryption process to reduce power consumption and increase speed by rearranging the transformation order and using combined lookup tables for SubBytes and Galois Multiplication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the traditional AES encryption process is used with separate SubBytes and MixColumns transformations, then the implementation is straightforward and easy to implement, but the encryption speed is slower and power consumption is higher

Engineering Contradiction:

Improveencryption speedVSAvoidtransformation complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent combines the SubBytes and MixColumns transformations into a single unified operation. Instead of executing SubBytes followed by MixColumns as separate steps, the invention merges them into one combined transformation that achieves the same cryptographic security while reducing the number of operational steps, thereby improving encryption speed and reducing power consumption.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The unified transformation serves multiple cryptographic functions simultaneously. The combined operation performs both the substitution function (SubBytes) and the diffusion function (MixColumns) in a single multi-functional operation, eliminating the need for separate dedicated circuits or instructions for each transformation.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If more clock cycles are used for AES encryption, then the transformation can be more thorough and secure, but the power consumption increases and processing efficiency decreases

Engineering Contradiction:

Improveencryption securityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

By merging SubBytes and MixColumns into a single combined transformation, the patent reduces the total number of clock cycles required for one AES round. This consolidation maintains the cryptographic security requirements of both transformations while executing them in fewer steps, thereby reducing power consumption.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The combined transformation enables continuous execution of cryptographic operations without the idle cycles or intermediate storage requirements between separate SubBytes and MixColumns operations. The unified operation processes data continuously through both transformation stages in one coherent execution flow.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS20250013430A1Reconfigurable architecture for improvement and optimization of advanced encryption standard

Publication Date: 2025.01.09 BOARD OF REGENTS FOR THE OKLAHOMA AGRI & MECHANICAL COLLEGE ACTING FOR & ON BEHALF OF OKLAHOMA STATE UNIV

AI summary

An improved implementation of an Advanced Encryption Standard is described, which in some aspects includes: a non-transitory computer-readable medium storing a first lookup table, a second lookup table, a plaintext, and a round key; a ShiftRows subassembly for shifting bytes of the plaintext; four combined SubBytes and MixColumns modules, including: a first data conversion engine for converting a first portion of the plaintext into a first result using the first lookup table; a second data conversion engine for converting a second portion of the plaintext into a second result using the second lookup table; and an even parity checker operating on the first result, the second result, and a third portion of the plaintext to produce a result array row; and an AddRoundKey subassembly operating on the round key and a result array formed by the result array rows from the four combined SubBytes and MixColumns modules.