AES Substitution Byte Unit Using Composite Field Arithmetic

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Solution Overview

Problem

Conventional AES encryption algorithm implementations in hardware face challenges with high computational complexity and large circuit area due to the substitution byte step, leading to a long critical path and increased circuit size.

Innovation Solution

A single round advanced encryption standard circuit module utilizing composite field arithmetic (CFA) with a pipeline structure, including a substitution byte/inverse substitution byte unit composed of multiple tier circuit units, reduces the critical path and circuit area by implementing multiplicative arithmetic circuits and multiplicative inverse element circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If lookup tables are used for substitution in AES encryption, then computational complexity is reduced, but circuit area increases significantly

Engineering Contradiction:
Improvecomputational complexityVSAvoidcircuit area
Core Design Contradiction:
Device complexityVSArea of stationary object

Solution Approach 1:

The patent transforms the substitution operation from a lookup table approach to a mathematical computation approach by changing the representation parameters. Specifically, it uses composite field arithmetic where elements are represented as polynomials over GF(2) rather than direct binary values, enabling substitution through algebraic operations that require minimal hardware resources while maintaining cryptographic security.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the mechanical/physical lookup table structure with a mathematical computation system. Instead of using a large memory array to store substitution values, the invention uses algebraic field operations (multiplication in composite fields) to compute substitution results dynamically, thereby eliminating the need for large static memory structures.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If conventional AES hardware implementation is used, then data encryption is achieved, but critical path length increases leading to reduced transmission rate

Engineering Contradiction:
Improvedata securityVSAvoiddata transmission rate
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent segments the substitution operation into multiple manageable stages using composite field arithmetic. By representing field elements as polynomials and breaking down multiplication operations into coefficient-wise computations followed by modular reduction, the critical path is divided into shorter segments that can be executed faster while maintaining the same cryptographic function.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic computation through algebraic operations that adapt to input values. The composite field arithmetic allows the substitution function to be computed on-the-fly based on the specific input element, rather than requiring a static lookup table, enabling faster response times and reduced critical path delays.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11750369B2Circuit module of single round advanced encryption standard
Publication Date: 2023.09.05 WISTRON NEWEB CORP
  • US11750369B2 patent drawing
  • US11750369B2 patent drawing
  • US11750369B2 patent drawing

AI summary

A single round advanced encryption standard circuit module includes a substitution byte/inverse substitution byte unit, configured to substitute elements of an input state array to generate an output state array and to respectively generate a first state array, a plurality of second state arrays, a third state array, a plurality of fourth state arrays and the output state array according to a first tier circuit unit, a second tier circuit unit, a third tier circuit unit, a fourth tier circuit unit and a fifth tier circuit unit; wherein the first state array, the plurality of second state arrays, the third state array and the plurality of fourth state arrays are represented by register-transfer level codes; wherein the substitution byte/inverse substitution byte unit is implemented by composite field arithmetic of sharing operators and operands.