All-Flash Array Server Cache Mirroring Architecture
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Solution Overview
Problem
The management of accessing Flash memory in all-flash array (AFA) servers is complex due to differences between SSDs and HDDs, leading to degraded performance, as existing control methods may become improper or invalid, necessitating a novel method and architecture to address these issues without introducing side effects.
Innovation Solution
A dual-node architecture for the AFA server, where each node has a processor, memory, and communication circuit, with write buffers and synchronized tail and head registers, enabling cache mirroring and efficient data writing verification between nodes, ensuring reliable data storage and access control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SSDs are used as storage media in AFA servers to replace HDDs, then data access speed and reliability are improved, but the complexity of managing and controlling Flash memory access increases
Solution Approach 1:
The system is divided into multiple independent nodes (first node and second node), each with its own processor, memory, and communication circuit. This segmentation allows each node to independently manage Flash memory access, reducing the overall management complexity while maintaining high data access speed through parallel operations.
Solution Approach 2:
The patent introduces communication circuits as intermediaries between nodes to coordinate Flash memory access. The communication circuits enable nodes to exchange information about access requests and status, allowing complex Flash memory management to be distributed and coordinated rather than centralized, thus reducing management complexity.
2Reliability
If control mechanisms are added to Flash memory controllers to ensure proper access control, then data integrity is improved, but the overall system performance is degraded
Solution Approach 1:
The patent combines the control functions for multiple Flash memory modules into a distributed control system where each node has its own processor managing local Flash memory. This merging of control functions at the node level eliminates the need for complex centralized control mechanisms, maintaining data integrity while preserving system performance.
Solution Approach 2:
Each node is equipped with its own processor and memory that can independently manage Flash memory access and verify data integrity. This self-service capability allows nodes to perform error checking and access control locally without requiring complex external control mechanisms, thus maintaining both data integrity and system performance.
3Reliability
If cache mirroring operation is implemented to copy data between nodes, then data reliability is improved, but the data writing time and processing overhead increase
Solution Approach 1:
The system performs cache mirroring by copying data between nodes during the write operation itself, rather than as a separate post-processing step. The first node receives data and simultaneously copies it to the second node's cache, ensuring data reliability is established early in the process without significant time penalty.
Solution Approach 2:
The patent implements continuous data writing and mirroring operations where the first processor writes data to the first write buffer while simultaneously initiating the mirroring process to the second node. This continuous operation ensures data reliability through mirroring while minimizing the time loss by overlapping the mirroring operation with the primary write operation.
Data Source
AI summary
The present invention provides a control method of a server, wherein the control method includes the steps of: setting a first node within the server as a master device; setting a second node within the server as a slave device; controlling the first node to receive data from another device via network; storing the data into a first write buffer within the first node; performing a cache mirroring operation to copy the data stored in the first write buffer into a second write buffer within the second node; setting a first tail register and a first head register within the first node, and setting a second tail register and a second head register within the second node; and referring to the first tail register and the first head register to determine if the data stored in the first write buffer is successful written into the second write buffer.