Image Scanner AFE Reset Circuit Using Processor Control Signals
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Solution Overview
Problem
Existing image scanning apparatuses face challenges in using Analog Front End (AFE) modules that require a reset signal, as they are not compatible with interfaces designed for AFEs that do not require a reset signal, limiting their integration and functionality.
Innovation Solution
An image scanning apparatus and method that utilize a processor to generate and provide control signals, including an enable signal and a clock signal or a control code signal, to reset AFEs, allowing for the use of both AFEs requiring and not requiring a reset signal through a unified interface, with a reset circuit unit employing NAND logic and RC filters to manage signal noise and timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an existing interface type using an AFE not requiring a reset signal is used, then the interface design is simple, but it is impossible to use an AFE requiring a reset signal
Solution Approach 1:
The interface is designed to universally support both AFE types (those requiring reset signals and those not requiring reset signals) through a single unified design. The processor generates control signals that can function as reset signals for AFEs requiring them, while maintaining compatibility with AFEs that do not require reset signals, thus achieving multi-functionality without increasing interface complexity
Solution Approach 2:
The processor acts as an intermediary between the control logic and the AFE, generating and managing control signals including reset signals. This intermediary role allows the system to accommodate different AFE types by mediating the signal generation and timing, enabling seamless integration of both AFE varieties through a unified interface
2Adaptability or versatility
If a reset circuit unit with NAND logic and RC filter is added to generate reset signals, then AFE compatibility is improved, but circuit complexity increases
Solution Approach 1:
The reset circuit unit is segmented into distinct functional components: a NAND logic circuit for generating the reset signal based on control signal timing, and an RC filter for noise reduction. This segmentation allows each component to perform its specific function efficiently while keeping the overall circuit design manageable and modular
Solution Approach 2:
The RC filter acts as an intermediary element between the NAND logic circuit and the AFE, serving to clean up the generated reset signal by reducing noise. This intermediary component ensures signal integrity without adding significant complexity, as it is a standard passive circuit element that can be easily integrated
Data Source
AI summary
An image scanning apparatus is provided. The image scanning apparatus includes an image sensor configured to scan image information of a manuscript, a converter configured to convert a signal scanned by the image sensor into a digital signal, a processor configured to control the converter by using a plurality of control signals and perform image-processing with respect to the signal converted into the digital signal, and a reset circuit unit configured to generate a reset signal by using the plurality of control signals and provide the converter with the generated reset signal.