Affine Image Processing Chip Architecture for Lower CPU Load
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Solution Overview
Problem
Conventional affine transformation functions implemented via software methods lead to excessive CPU resource occupancy, causing high CPU load.
Innovation Solution
An image processing component utilizing hardware-based address generation, source image reading, and interpolation calculation units to perform affine transformations, reducing the need for CPU execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software method is used to implement affine transformation function, then implementation flexibility is maintained, but CPU resource occupancy increases excessively
Solution Approach 1:
The patent replaces the software-based affine transformation implementation with a dedicated hardware processing component. This hardware component includes an address generation unit, a pixel reading unit, and an interpolation calculation unit that work together to perform warp operations in hardware rather than through CPU-executed software, thereby reducing CPU resource occupancy while maintaining implementation flexibility through configurable hardware parameters.
2Ease of manufacture
If software method is used for affine transformation, then ease of implementation is maintained, but processing speed decreases due to CPU load
Solution Approach 1:
The patent divides the affine transformation process into three distinct hardware units: an address generation unit that calculates source point coordinates and memory addresses, a pixel reading unit that reads pixel values from memory, and an interpolation calculation unit that performs the actual warp calculation. This segmentation allows each unit to be optimized independently and operate in parallel, improving processing speed while maintaining ease of implementation through modular design.
Solution Approach 2:
The patent introduces an address generation unit as an intermediary component between the pixel reading unit and the interpolation calculation unit. This intermediary unit pre-calculates source point coordinates and generates memory reading addresses, allowing the pixel reading unit to efficiently retrieve required pixel values without burdening the CPU, thereby improving overall processing speed.
3Use of energy by moving object
If hardware-based processing is implemented, then CPU resource occupancy is reduced, but device complexity increases
Solution Approach 1:
The patent designs a universal hardware processing component that can handle various affine transformation operations through configurable parameters. The address generation unit, pixel reading unit, and interpolation calculation unit work together as an integrated multi-functional system that can process different image sizes, resolution, and transformation parameters without requiring separate hardware for each operation, thereby reducing overall device complexity while maintaining low CPU resource occupancy.
Data Source
AI summary
Provided are image processing assembly, chip, image processing method and storage medium. Image processing assembly includes address generation unit, source image reading unit and interpolation calculation unit, address generation unit is connected to source image reading unit, which is connected to interpolation calculation unit; address generation unit calculates source point coordinates of target pixel point in source image according to coordinates of target pixel point, determines, according to source point coordinates, multiple neighborhood integer coordinates corresponding to source point coordinates, and determines reading address of each neighborhood integer coordinate in memory according to multiple neighborhood integer coordinates; source image reading unit obtains, according to read address of each neighborhood integer coordinate in memory, pixel value corresponding to each neighborhood integer coordinate; and interpolation calculation unit performs interpolation calculation according to pixel value, to obtain pixel value of target pixel point in affine image which corresponds to source image.