Linear Regression Bit-Length Control for Affine Motion Models
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Solution Overview
Problem
Existing video coding techniques for linear regression-based affine merge candidate derivation often result in bit lengths that are impractical or impossible to implement in hardware, leading to data overflows and inconsistent decoding across different decoders.
Innovation Solution
Implement bit length control for input variables and intermediate results to meet a commonly defined threshold, limiting bit lengths to 64 bits or below, thereby facilitating hardware implementation of video coders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If linear regression operation is performed without bit length control, then calculation precision is improved, but data overflow occurs making hardware implementation impossible
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the bit length of intermediate calculation results during the linear regression operation. Instead of using fixed precision throughout, the system modifies precision parameters at different stages of calculation to balance accuracy with hardware implementation constraints, preventing overflow while maintaining sufficient precision for video coding applications.
Solution Approach 2:
The patent segments the linear regression calculation into multiple stages, applying different bit length controls to different intermediate results. By dividing the calculation process and applying precision control selectively to specific intermediate values (such as sum of products, determinant calculations, and final parameter derivation), the system maintains necessary precision where critical while limiting bit length in less critical intermediate steps.
2Ease of manufacture
If bit length is limited to 64 bits for hardware implementation, then hardware feasibility is improved, but data overflow risk increases
Solution Approach 1:
The patent implements beforehand cushioning by pre-establishing bit length control mechanisms and overflow prevention rules before the linear regression operation executes. The system prepares lookup tables, pre-calculates safe bit length thresholds, and sets up clipping mechanisms in advance to cushion against potential overflow conditions, ensuring reliable and consistent decoding results across different hardware implementations.
3Ease of manufacture
If bit length control is applied to intermediate results, then hardware implementation is enabled, but calculation complexity increases
Solution Approach 1:
The patent employs cheap short-living objects by using simplified bit length control mechanisms that are computationally inexpensive and easily implementable in hardware. Instead of complex adaptive precision algorithms, the system uses straightforward bit truncation, rounding, or clipping operations that can be implemented with simple logic circuits, accepting minor precision loss in exchange for dramatically reduced implementation complexity.
Data Source
AI summary
An example device for coding video data includes memory configured to store the video data and one or more processors communicatively coupled to the memory. The one or more processors are configured to reduce a bit length of one or more input variables for a linear regression operation to generate one or more reduced bit length input variables, the input variables including at least one of a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of subblocks. The one or more processors are configured to perform the linear regression operation and derive an affine motion model based on the performing the linear regression on the one or more reduced bit length input variables. The one or more processors are configured to code a current block of the video data based on the affine motion model.