AFSM Output Masking Topology for Glitch-Free Asynchronous Logic
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Solution Overview
Problem
Combinatorial logic circuits are prone to glitches due to asynchronous operations of logic gates, leading to unwanted output switchings and increased power consumption, noise injection, and design complexity, which existing path delay balancing techniques may not adequately address without increasing overall propagation delay.
Innovation Solution
An asynchronous finite state machine design that includes a core with state cells and a delay circuit in the feedback path to manage state overlap time, ensuring it exceeds the tree propagation time, and an output net with a balanced logic tree cascaded with an additional logic tree to prevent glitches by inserting delays strategically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If path delay balancing techniques are applied to eliminate hazards, then glitch prevention is improved, but overall propagation delay increases
Solution Approach 1:
The patent applies delay elements selectively only to non-critical signal paths within the combinatorial logic circuit, rather than uniformly balancing all paths. This localized approach masks hazards in specific problematic paths without increasing the overall propagation delay determined by critical paths, thus preventing glitches while maintaining fast response times.
Solution Approach 2:
The patent introduces delay elements in advance on specific signal paths to pre-synchronize arrivals of signals at logic gates. By preliminarily adjusting the timing of non-critical paths before hazards can occur, the circuit avoids glitches without requiring post-design path balancing that would increase overall delay.
2Speed
If asynchronous operation is used for fast response, then speed is improved, but hazards causing glitches increase
Solution Approach 1:
The patent maintains asynchronous operation for overall fast response while locally applying delay elements only to specific non-critical paths where hazards occur. This selective synchronization preserves the speed advantages of asynchronous operation for critical signals while eliminating hazards in problematic paths, achieving both fast response and reliability.
3Reliability
If delay elements are added to mask hazards, then glitch prevention is improved, but device complexity increases
Solution Approach 1:
The patent minimizes device complexity by applying delay elements only to specific non-critical paths where hazards are identified, rather than uniformly modifying the entire circuit. This localized hazard masking approach reduces the number of added components and maintains circuit simplicity while effectively preventing glitches.
Solution Approach 2:
The patent uses delay elements as intermediary components inserted strategically in signal paths to mediate timing differences without fundamentally altering the circuit architecture. These intermediary delay elements smoothly synchronize signals and mask hazards while adding minimal complexity to the overall device structure.
Data Source
AI summary
An AFSM core includes a destination state-cell generating a destination state-signal, and a source state-cell generating a source state-signal and causing transition of the source state-signal in response to an acknowledgement indicating transition of the destination state-signal. The acknowledgment is communicated through a delay. A state-overlap occurs between transition of the destination state-signal and transition of the source state-signal. An output-net includes a balanced logic-tree receiving inputs, including the destination state-signal, from the core, and an additional logic-tree cascaded with the balanced logic-tree to form an unbalanced logic-tree so an input to the additional logic-tree is provided by output from the balanced logic-tree and another input receives the source state-signal. Tree propagation time occurs between receipt of a transition in the destination state-signal by the balanced logic-tree and a resulting transition of the output from the balanced logic-tree. The delay circuit causes the state-overlap to exceed the tree propagation time.