Age-Adaptive Nonvolatile Memory Read Control for Cell Coupling
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Solution Overview
Problem
The reliability and accuracy of nonvolatile memory devices degrade over time due to increased coupling between memory cells and repeated program/erase operations, leading to reduced data retention and increased non-uniformity, which limits their lifetime.
Innovation Solution
A memory system with a memory controller that applies specific signals to perform error checking and correction operations, and selectively performs reliability improvement operations based on the number of program/erase cycles to maintain data accuracy and extend device lifetime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell technology is used to store more data in limited cells, then storage density is improved, but dispersion characteristics and uniformity of memory cells deteriorate
Solution Approach 1:
The patent applies different read operations based on the age of specific memory blocks. Younger blocks use standard read operations while older blocks use enhanced read operations with additional signals to compensate for coupling effects. This local differentiation allows the system to maintain high storage density through multi-level cell technology while addressing the dispersion characteristics issue in affected areas without compromising overall performance.
2Adaptability or versatility
If program/erase operations are repeated to update data, then data freshness is improved, but dispersion characteristics are degraded and lifetime is reduced
Solution Approach 1:
The patent implements a read-before-write operation sequence where data is read from a memory block before programming new data. This preliminary read operation allows the system to assess the current state of the memory block and adjust subsequent write operations accordingly. By performing this preliminary action, the system can reduce the impact of repeated program/erase operations on dispersion characteristics while maintaining data freshness, thereby extending memory lifetime.
3Speed
If standard read operations are used for all memory blocks, then read speed is maintained, but read accuracy deteriorates for older blocks
Solution Approach 1:
The patent dynamically adjusts read operations based on memory block age. The system tracks the number of program/erase cycles and automatically switches between standard and enhanced read operations for different blocks. This dynamic adaptation allows the system to maintain high read speed for younger blocks while ensuring high read accuracy for older blocks that are more susceptible to coupling effects, thus resolving the contradiction between speed and precision.
4Measurement precision
If enhanced read operations with coupling data reading are applied to all blocks, then read accuracy is improved, but operation complexity and time increase
Solution Approach 1:
The patent applies enhanced read operations selectively only to memory blocks that have undergone a sufficient number of program/erase cycles and are therefore prone to coupling effects. Younger blocks continue to use simple standard read operations. This localized application of complex operations only where necessary maintains high read accuracy for affected blocks while avoiding the operational complexity and time overhead across the entire memory array, thus resolving the contradiction between accuracy and complexity.
Data Source
AI summary
Integrated circuit memory systems include a nonvolatile memory device having an array of nonvolatile memory cells therein and a memory controller, which is electrically coupled to the nonvolatile memory device. The memory controller is configured to apply signals to the nonvolatile memory device that cause the nonvolatile memory device to modify how data is read from the array of nonvolatile memory cells. This modification occurs in response to detecting an increase in an age of the nonvolatile memory device. The age of the nonvolatile memory device may be determined by keeping a count of how many times the nonvolatile memory device has undergone a program/erase cycle.