Aggregate SMP Architecture for Scalable Memory Access
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Solution Overview
Problem
Conventional symmetric multiprocessor (SMP) systems face performance diminishing returns as they scale due to increased coherency messaging traffic and memory namespace exhaustion, limiting their ability to efficiently process workloads across multiple processor cores.
Innovation Solution
An aggregate SMP data processing system architecture that includes multiple SMP computers with restricted access memory pools, allowing for hardware-managed load/store coherent, ordered access across different SMP computers, reducing coherency messaging overhead and enabling real address aliasing to extend memory namespace.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of processing units in an SMP system is increased to provide greater processing power, then the processing capability is improved, but the coherency messaging traffic on the system interconnect increases approximately as the square of system scale, resulting in diminishing return in performance
Solution Approach 1:
The patent divides a large SMP system into multiple smaller SMP computers, each with its own processing units and memory pools. This segmentation reduces the coherency messaging traffic within each smaller computer while maintaining the overall processing power through the aggregation of multiple computers connected via an interconnect fabric.
Solution Approach 2:
The patent introduces an interconnect fabric as an intermediary between multiple SMP computers, enabling them to function as a single larger SMP system. This intermediary structure allows for efficient communication and data sharing while managing coherency across the distributed system without geometric growth in messaging traffic.
2Power
If the number of processing units in an SMP system is increased to provide greater processing power, then the processing capability is improved, but the memory namespace shared by all processor cores becomes exhausted
Solution Approach 1:
The patent segments the memory namespace into separate memory pools associated with each SMP computer. Each processing unit has access to a dedicated memory pool, which prevents namespace exhaustion while allowing the system to scale by adding more memory pools through additional SMP computers.
Solution Approach 2:
The patent extends the memory architecture from a single shared namespace to a multi-dimensional memory hierarchy with multiple memory pools across different SMP computers. This dimensional expansion allows the system to accommodate vastly increased memory capacity while maintaining efficient access patterns.
3Reliability
If multiple processor cores access updated copies of memory blocks to maintain coherence, then data consistency is improved, but the coherency messaging traffic increases geometrically with system scale
Solution Approach 1:
The patent segments the coherency management scope by creating separate memory pools for each SMP computer. Coherency messaging is confined to within-computer transactions rather than spanning the entire distributed system, dramatically reducing the geometric growth of messaging traffic while maintaining data consistency through localized cache coherency protocols.
Data Source
AI summary
A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.