Aggregated Memory Interfaces for Compact SoC HBM Support
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Solution Overview
Problem
The integration of multiple high bandwidth memory (HBM) modules in System-on-Chip (SoC) circuits requires a larger periphery, increasing the size and cost of the SoC die, necessitating a solution that maintains compact size while enhancing memory capacity and reducing costs.
Innovation Solution
The implementation of a system-on-chip (SoC) die connected to a first memory interface via an interposer substrate with a buffer die housing a shared second memory interface, allowing multiple memory modules to communicate through a consolidated interface, thereby optimizing the SoC's size and reducing the need for multiple independent interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple independent memory interfaces are allocated on the SoC die to connect with multiple HBM modules, then memory capacity and bandwidth are improved, but the SoC die size and cost increase
Solution Approach 1:
Multiple memory interfaces are merged into a single shared memory interface on the buffer die. The buffer die consolidates multiple interface circuits that would otherwise be distributed across the SoC die, allowing multiple HBM modules to share one interface location. This merging reduces the periphery required on the SoC die while maintaining support for multiple memory modules.
Solution Approach 2:
A buffer die is introduced as an intermediary component between the SoC die and multiple HBM modules. The buffer die contains the shared memory interface and routing circuits, mediating the connection between the SoC die and multiple memory modules. This intermediary approach allows the SoC die to maintain a compact size while still supporting multiple high-bandwidth memory modules through the buffer's routing capabilities.
2Adaptability or versatility
If multiple independent memory interfaces are allocated on the SoC die, then connectivity to multiple HBM modules is improved, but manufacturing cost increases
Solution Approach 1:
Multiple memory interface circuits are merged into a single shared interface location on the buffer die. This consolidation reduces the complexity of manufacturing the SoC die, as fewer independent interface circuits need to be fabricated and routed on the SoC die itself. The buffer die absorbs the complexity of supporting multiple interfaces, simplifying the SoC die manufacturing process.
Solution Approach 2:
The system is segmented into three separate components: the SoC die, the buffer die, and multiple HBM modules. By separating the memory interface functionality into a dedicated buffer die, the complexity of supporting multiple interfaces is isolated to a single component. This segmentation allows each die to be optimized for its specific function, reducing overall manufacturing complexity and cost.
3Adaptability or versatility
If the periphery of the SoC die is increased to accommodate more memory interfaces, then the number of supported HBM modules is improved, but the compactness of the SoC design is degraded
Solution Approach 1:
The buffer die serves as an intermediary that handles the complexity of connecting to multiple HBM modules. This allows the SoC die to maintain a compact, simple design with minimal periphery requirements, while the buffer die absorbs the routing and interface complexity needed to support multiple memory modules.
Solution Approach 2:
The solution moves the interface complexity from the two-dimensional plane of the SoC die periphery to a separate buffer die component. By relocating the interface circuits to a different physical location (the buffer die), the SoC die can maintain its compact footprint while still supporting multiple HBM modules through the buffer's routing capabilities.
Data Source
AI summary
A system includes a substrate comprising a first circuit. The system also includes an integrated circuit formed in a first die disposed on the substrate. The integrated circuit includes at least a processor, a controller, and a first memory interface. The first memory interface is located in a first edge of the first die and is configured to couple to the first circuit. The system also includes a first buffer circuit formed in a second die disposed on the interposer substrate adjacent to the first edge of the first die. The first buffer circuit includes a second memory interface configured to couple to the first connection circuit. The system further includes multiple memory modules disposed on the second die. Each of the multiple memory modules at least partially share the second memory interface to communicate with the integrated circuit.