Aggregated MMU with Shared Translation Cache
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Solution Overview
Problem
Current MMU architectures, such as monolithic and distributed MMUs, are ineffective in reducing chip area costs while maintaining performance, especially for mid- and high-performance processors, due to duplication of components and interconnect requirements.
Innovation Solution
The introduction of aggregated MMUs, which feature a mix of dedicated and shared elements, including input and output data paths, transaction buffers, translation caches, and hardware page table walkers, configured to perform memory address translation and apply Quality-of-Service (QoS) arbitration to efficiently manage resources and prevent monopolization by any single client.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If monolithic MMUs are provided for each high-performance client, then processing performance is improved, but chip area increases due to duplication of constituent elements
Solution Approach 1:
The MMU is divided into multiple independent processing pipelines, each capable of handling transactions from different clients. Each pipeline includes dedicated input buffers, translation logic, and output buffers, allowing parallel processing while sharing common resources like the translation cache and page table walkers, thus reducing overall chip area while maintaining high performance
Solution Approach 2:
The aggregated MMU design creates a universal MMU structure that can service multiple traffic-producing clients through a single unified architecture. The common translation cache and page table walkers serve all clients, eliminating the need for duplicate resources while maintaining the ability to handle high-performance transactions from multiple sources simultaneously
2Area of stationary object
If monolithic MMUs are shared among low-performance clients, then chip area is reduced, but performance degrades
Solution Approach 1:
The MMU architecture implements dynamic resource allocation where translation cache entries and page table walker resources can be flexibly allocated based on client performance requirements. High-performance clients receive dedicated or prioritized access to translation resources, while low-performance clients share resources, allowing the system to adapt resource distribution to actual performance needs rather than using a static allocation
3Area of stationary object
If distributed MMU architecture is used with client MMU units, then chip area is reduced for low-performance processors, but scaling to mid- and high-performance processors is limited due to translation cache replication and interconnect requirements
Solution Approach 1:
The aggregated MMU merges the translation cache and page table walker resources from multiple distributed MMU units into a single shared resource pool. This consolidation eliminates the need for replication of translation cache entries across multiple units and reduces interconnect requirements, while still providing the ability to service multiple clients with high performance through the unified architecture
Data Source
AI summary
Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.