Aggressive Quick-Pass Multiphase Programming for Non-Volatile Memory
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Solution Overview
Problem
Existing methods for programming multi-level memory cells, such as foggy-fine programming, require additional hardware resources and increase costs due to the need for high endurance non-volatile memory as a cache, limiting capacity, endurance, performance, and cost-effectiveness of storage devices.
Innovation Solution
Implementing an aggressive quick-pass programming scheme that separates voltage distribution states during the second programming phase of a multiphase programming method, allowing for direct read-back of data from programmed memory cells without the need for a cache, thereby simplifying storage device design and optimizing space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If foggy-fine programming approach is used to program QLC memory cells, then programming precision is improved, but device complexity and cost increase due to requiring SLC cache
Solution Approach 1:
The programming process is divided into two phases: MLC programming phase and QLC programming phase. The MLC phase programs 2 bits per cell with wider voltage distributions, while the QLC phase programs additional 2 bits to achieve 4 bits per cell with narrower voltage distributions. This segmentation allows each phase to use optimized programming parameters, achieving high precision without requiring SLC cache.
Solution Approach 2:
The patent changes programming parameters between phases: in the MLC phase, higher programming voltages and wider voltage distributions are used for faster programming, while in the QLC phase, lower programming voltages and narrower voltage distributions are used for higher precision. This parameter transformation enables precision programming without requiring expensive SLC cache hardware.
2Reliability
If SLC cache is reserved for foggy phase data storage, then data integrity during power failure is improved, but storage capacity and cost effectiveness deteriorate
Solution Approach 1:
The MLC programming phase is performed first to establish readable intermediate states before QLC programming begins. This preliminary action ensures that if power fails during QLC programming, the data remains intact in the MLC states and can be recovered, eliminating the need for separate SLC cache while maintaining data integrity.
Solution Approach 2:
The memory cells themselves serve as the storage medium for intermediate MLC programming data, rather than requiring separate SLC cache. The programmed MLC states naturally preserve data during power failures, allowing the system to be self-sufficient without additional cache hardware, thereby maximizing storage capacity.
3Loss of substance
If MLC programming is performed in first pass followed by QLC programming, then buffer requirements are reduced, but voltage distribution overlap increases
Solution Approach 1:
The patent dynamically adjusts programming parameters during the QLC phase based on the state of previously programmed MLC distributions. By monitoring voltage distribution overlap and adapting programming voltages and pulse widths in real-time, the system maintains separation between voltage distributions while eliminating buffer requirements.
Solution Approach 2:
Verification operations are performed between programming pulses to monitor the state of memory cells and detect voltage distribution overlap. This feedback mechanism allows the control circuitry to adjust subsequent programming parameters to prevent overlap, ensuring precise voltage distribution separation without requiring additional buffer storage.
Data Source
AI summary
A multiphase programming scheme for programming a plurality of memory cells of a data storage system includes a first programming phase in which a first set of voltage distributions of the plurality of memory cells is programmed by applying a first plurality of program pulses to word lines of the plurality of memory cells, and a second programming phase in which a second set of voltage distributions is programmed by applying a second plurality of program pulses to the word lines of the plurality of memory cells. The second programming phase includes maintaining a margin of separation between two adjacent voltage distributions of the second set of voltage distributions after each of the second plurality of program pulses. This scheme achieves better margin using an aggressive quick pass approach, which helps with data recovery in case of power loss events.