Digital Aging Sensor Using TDC Delay Comparison

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Solution Overview

Problem

Conventional aging sensor solutions for electronic systems provide inaccurate measurements of circuit path degradation due to reliance on frequency shift measurements, which do not account for actual aging-induced signal degradation.

Innovation Solution

A digital aging sensor that measures the delay difference between an unaged reference delay path and an aged delay path, using a time-to-digital converter (TDC) to accurately track circuit path degradation, with self-centering calibration logic and asynchronous implementation to mitigate external disturbances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If frequency shift measurement is used to track aging, then the measurement process is simple, but the measurement precision is insufficient

Engineering Contradiction:
Improveaging measurement precisionVSAvoidsensor structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The sensor is segmented into two separate delay paths: a reference delay path that remains unaged and an aged delay path that experiences aging. This segmentation allows independent measurement of aging effects by comparing the two paths, thereby improving measurement precision without requiring complex aging models

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A time-to-digital converter (TDC) is introduced as an intermediary component to accurately measure the delay difference between the reference and aged delay paths. The TDC provides high-resolution timing measurement capability that directly improves aging measurement precision while maintaining relatively simple sensor structure

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If conventional aging sensor is used, then the device complexity is low, but the reliability of aging tracking is insufficient

Engineering Contradiction:
Improveaging tracking reliabilityVSAvoidsensor circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The circuit is divided into parallel reference and aged delay paths, allowing the aged path to accurately track actual circuit aging while the reference path provides a stable baseline. This segmentation ensures that aging measurements reflect true circuit degradation, improving reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The sensor implements feedback mechanisms where the measured delay difference is used to update aging information, which can then be used to adjust operating parameters or trigger maintenance actions. This closed-loop feedback improves the reliability of aging tracking by continuously monitoring and responding to actual aging conditions

Inventive Principle:
Principle #23Feedback

3Measurement precision

If frequency-based aging measurement is implemented, then the ease of operation is high, but the measurement precision of signal degradation is insufficient

Engineering Contradiction:
Improvesignal degradation measurementVSAvoidsensor operation simplicity
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The sensor replaces frequency-based measurement with direct time-domain measurement using a time-to-digital converter. This substitution provides higher precision for signal degradation measurement by directly measuring delay differences in the time domain, while the automated TDC operation maintains ease of use

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentEP4625821A1Digital aging sensor
Publication Date: 2025.10.01 INTEL CORP
  • EP4625821A1 patent drawingFigure 1A
  • EP4625821A1 patent drawingFigure 1B~1C
  • EP4625821A1 patent drawingFigure 2

AI summary

Some embodiments include an apparatus having a circuit, the circuit including an output node to provide a signal; a first delay line including an input node coupled to the output node of the circuit, and an output node; a second delay line including an input node coupled to the output node of the circuit, and an output node; and time-to-digital converter (TDC) including a first input node coupled to the output node of the first delay line, and a second input node coupled to the output node of the second delay line.