Agnostic Runtime Architecture Conversion Tables
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Solution Overview
Problem
Current processor architectures face inefficiencies in handling multiple threads due to the need for context switching, which is resource-intensive and complex, especially when the number of software threads exceeds hardware-supported threads, and do not effectively support fine-grain parallelism.
Innovation Solution
An agnostic runtime architecture system that includes a system emulation/virtualization converter, application code converter, and system converter, utilizing conversion tables and a cache to translate guest instructions into native instructions, allowing for efficient execution and optimization of code without the need for frequent context switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If hardware duplicates all architecture state elements for each supported thread, then context switch is eliminated, but area, power and complexity increase
Solution Approach 1:
The patent segments the architecture state into multiple save areas (first save area, second save area, etc.) that can be independently accessed. Instead of duplicating all state elements for each thread, the system divides the state storage into discrete segments that can be switched between threads efficiently, reducing the complexity of full duplication while maintaining fast context switching.
Solution Approach 2:
The patent implements preliminary action by pre-positioning thread state information in save areas before context switching is needed. The thread information storage unit stores thread identifiers and associated state data in advance, allowing the context switch mechanism to quickly retrieve and restore state without performing complex operations during the actual switch, thus eliminating context switch time penalties.
2Loss of time
If hardware supports limited number of threads with duplicated state, then context switch is avoided, but number of supported threads is limited
Solution Approach 1:
The patent creates a universal context switch mechanism that can handle any number of threads through the thread information storage unit. This unit stores thread identifiers and state information in a scalable manner, allowing the same hardware structure to support an unlimited number of threads rather than requiring dedicated duplication for each thread. The save areas and restore logic serve multiple threads universally, increasing adaptability while maintaining fast switching.
3Adaptability or versatility
If context switch is performed frequently, then thread management is achieved, but processing overhead increases
Solution Approach 1:
The patent extracts the thread management overhead from the critical execution path by implementing a dedicated thread information storage unit and simplified save/restore mechanism. The context switch operation is extracted into a separate, optimized pathway that uses pre-stored thread information rather than performing full state copying during execution. This separation reduces processing overhead by eliminating redundant operations while maintaining comprehensive thread management capability.
Data Source
AI summary
A system for an agnostic runtime architecture is disclosed. The system includes a system emulation/virtualization converter, an application code converter, and a system converter wherein the system emulation/virtualization converter and the application code converter implement a system emulation process, and wherein the system converter implements a system conversion process for executing code from a guest image. The system converter further comprises a guest fetch logic component for accessing a plurality of guest instructions, a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling the plurality of guest instructions into a guest instruction block, and a plurality of conversion tables including a first level conversion table and a second level conversion table coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block. The system further includes a native cache coupled to the conversion tables for storing the corresponding native conversion block, a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache, and in response to the hit the conversion look aside buffer forwards the translated native instruction for execution.