Ahead Predictable Branch Trace Cache for Pipeline Bubble Elimination
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Solution Overview
Problem
Conventional branch target instruction trace cache approaches fail to effectively predict branch instructions, leading to pipeline bubbles and reduced processor performance and cache usage efficiency, especially in handling consecutive jump instruction streams.
Innovation Solution
The method involves an ahead predictable branch instruction trace cache (APBTC) that uses a prediction table based on branch history information to store target instructions for direct jumps, allowing quick fetching of required instructions and predicting branch instructions, thereby eliminating pipeline bubbles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional branch target instruction trace cache is used to store target instructions, then address redirection bubbles are alleviated, but pipeline bubbles from branch prediction remain and processor performance is limited
Solution Approach 1:
The patent applies preliminary action by performing branch prediction in advance during the first pipeline stage. The prediction table pre-calculates whether branch instructions will jump and stores this prediction information before the instruction execution phase, allowing the processor to prepare for address redirection ahead of time and eliminate pipeline bubbles.
Solution Approach 2:
The patent segments the branch prediction process into two distinct pipeline stages: first level pipeline stage for initial branch prediction using the prediction table, and second level pipeline stage for fetching instructions based on prediction results. This segmentation allows independent optimization of each stage and resolves the contradiction by handling address redirection and branch prediction separately.
2Speed
If conventional BTC stores target instructions in cache, then cache access speed improves, but consecutive jump instruction streams cannot be handled effectively
Solution Approach 1:
The patent implements feedback by using the prediction table to store and reuse branch prediction results. When the same branch instruction is encountered again, the pre-stored prediction information is retrieved and applied, allowing the system to adapt to recurring jump patterns and handle consecutive jump instruction streams effectively while maintaining fast cache access.
Solution Approach 2:
The prediction table pre-computes and stores branch prediction outcomes for frequently executed branch instructions. This preliminary action enables the processor to quickly retrieve prediction results without re-computing them, thereby maintaining high instruction fetch speed while improving adaptability to handle various jump instruction patterns including consecutive jumps.
3Device complexity
If branch prediction is not performed in BTC, then cache structure remains simple, but pipeline bubbles from branch instructions cannot be eliminated
Solution Approach 1:
The patent segments the prediction structure from the cache structure by introducing a separate prediction table that works in conjunction with the existing branch target instruction trace cache. This segmentation allows branch prediction functionality to be added without fundamentally redesigning the cache structure, maintaining relative simplicity while eliminating pipeline bubbles through coordinated operation of the prediction table and cache.
Data Source
AI summary
Disclosed in the present invention are an ahead prediction method and branch instruction trace cache for direct jumping. The branch trace cache comprises: a prediction table based on historical branch information, which prediction table is used for implementing two jumping predictions, wherein the prediction table based on the historical branch information comprises the current branch prediction table and an ahead branch trace cache prediction table; a branch trace cache, which comprises a plurality of entries, each entry storing a plurality of consecutive instructions, and the plurality of consecutive instructions including a branch instruction, wherein each entry serves as a branch trace cache item, and comprises: a target instruction of the branch instruction, a sequential address of the target instruction of the branch instruction, a jump address of the target instruction of the branch instruction, and a tag; and a system cache.