Aho-Corasick Memory Circuit Node Tree Compression

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Solution Overview

Problem

Conventional Aho-Corasick type character recognition automatons require significant memory and hardware resources for database construction and data transfer, making them inefficient for applications like computer virus signature recognition.

Innovation Solution

A memory circuit for an Aho-Corasick type character recognition automaton is implemented in hardware form, using a node tree with successive transitions stored in memory, where each node corresponds to a recognized character string, and nodes are addressable with a base node and relative shift, reducing memory requirements and clock transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional Aho-Corasick automaton is implemented with complete node tree in memory, then character recognition functionality is achieved, but memory size becomes excessively large (exceeding 100 Mb)

Engineering Contradiction:
Improvecharacter recognition functionalityVSAvoidmemory size
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments the node tree into two distinct storage structures: a compressed trie for common prefixes and a suffix tree for pattern-specific paths. This segmentation allows each structure to be optimized independently, reducing overall memory consumption while maintaining recognition functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the automaton are stored with different levels of detail and compression. Frequently accessed nodes use compact representations, while less frequent patterns use more detailed storage. This local optimization reduces average memory usage without sacrificing recognition accuracy.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If Aho-Corasick automaton is implemented in software form with database transfer via buses, then flexibility is maintained, but data transfer time becomes considerable

Engineering Contradiction:
Improvesoftware implementation flexibilityVSAvoiddata transfer time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent replaces the mechanical bus-based data transfer system with a hardware-implemented finite state machine that performs pattern matching directly in parallel. This substitution eliminates sequential data transfer delays while maintaining the adaptability of the Aho-Corasick algorithm through configurable hardware logic.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Adaptability or versatility

If complete node tree is constructed for pattern recognition, then all patterns can be recognized, but hardware resources become excessively large

Engineering Contradiction:
Improvemulti-pattern recognition capabilityVSAvoidhardware resources
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a nested structure where the compressed trie is embedded within the suffix tree framework. Common prefixes are stored in the compact trie structure, while pattern-specific variations are stored in the suffix tree. This nesting allows the hardware to recognize multiple patterns using shared structural elements, reducing overall hardware complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS8849841B2Memory circuit for Aho-corasick type character recognition automaton and method of storing data in such a circuit
Publication Date: 2014.09.30 STMICROELECTRONICS FRANCE
  • US8849841B2 patent drawing
  • US8849841B2 patent drawing
  • US8849841B2 patent drawing

AI summary

A memory circuit for an Aho-Corasick type character recognition automaton uses a node tree for recognizing predetermined strings of characters in an incoming data stream. The recognization is based upon successive transitions in the node tree stored in memory in which each node corresponds to a recognized sequence of a character string. At least part of the nodes are related to a consecutive node by a valid transition, from an initial state to terminal states, with each one corresponding to a recognized character string This memory circuit includes first sets of consecutive memory addresses defining respectively strings of consecutive nodes accessible sequentially during successive transitions to a terminal state, and second sets of memory addresses defining multiple nodes each pointing to several states.